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GHSA-XRFH-4HQ6-C36G

Vulnerability from github – Published: 2026-08-15 06:32 – Updated: 2026-08-17 06:33
VLAI
Details

In the Linux kernel, the following vulnerability has been resolved:

net: mvneta: re-enable percpu interrupt on resume

On Marvell MPIC platforms (Armada 370/XP/38x), mvneta uses a percpu IRQ disable/enable scheme for NAPI: the ISR (mvneta_percpu_isr) calls disable_percpu_irq() to mask the MPIC per-CPU interrupt and schedules NAPI poll, which calls enable_percpu_irq() on completion to unmask.

If suspend occurs while NAPI poll is pending (between disable_percpu_irq in the ISR and enable_percpu_irq in poll completion), the interrupt is never re-enabled:

  1. mvneta_percpu_isr: disable_percpu_irq() + napi_schedule() => MPIC masked, percpu_enabled cpumask bit cleared
  2. NAPI poll does not complete before suspend proceeds (on PREEMPT_RT this is highly likely since softirqs run in ksoftirqd which gets frozen; on non-RT it can happen when softirq processing is deferred to ksoftirqd)
  3. mvneta_stop_dev => napi_disable(): cancels the pending poll without executing the completion path
  4. suspend_device_irqs => IRQCHIP_MASK_ON_SUSPEND: masks MPIC (already masked, but records IRQS_SUSPENDED)
  5. Resume: mpic_resume checks irq_percpu_is_enabled() => false (bit was cleared in step 1) => skips unmask
  6. mvneta_start_dev only restores device-level INTR_NEW_MASK, does not touch the MPIC per-CPU mask

Result: MPIC per-CPU interrupt stays masked permanently. The NIC generates interrupts (INTR_NEW_CAUSE != 0) but the CPU never receives them, causing complete loss of network connectivity.

Fix by calling on_each_cpu(mvneta_percpu_enable) in the resume path to unconditionally unmask the MPIC per-CPU interrupt regardless of pre-suspend state.

Severity
7.5 (High)
CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:H
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{
  "affected": [],
  "aliases": [
    "CVE-2026-72409"
  ],
  "database_specific": {
    "cwe_ids": [],
    "github_reviewed": false,
    "github_reviewed_at": null,
    "nvd_published_at": "2026-08-15T06:22:14Z",
    "severity": "HIGH"
  },
  "details": "In the Linux kernel, the following vulnerability has been resolved:\n\nnet: mvneta: re-enable percpu interrupt on resume\n\nOn Marvell MPIC platforms (Armada 370/XP/38x), mvneta uses a percpu\nIRQ disable/enable scheme for NAPI: the ISR (mvneta_percpu_isr) calls\ndisable_percpu_irq() to mask the MPIC per-CPU interrupt and schedules\nNAPI poll, which calls enable_percpu_irq() on completion to unmask.\n\nIf suspend occurs while NAPI poll is pending (between\ndisable_percpu_irq in the ISR and enable_percpu_irq in poll\ncompletion), the interrupt is never re-enabled:\n\n  1. mvneta_percpu_isr: disable_percpu_irq() + napi_schedule()\n     =\u003e MPIC masked, percpu_enabled cpumask bit cleared\n  2. NAPI poll does not complete before suspend proceeds\n     (on PREEMPT_RT this is highly likely since softirqs run in\n     ksoftirqd which gets frozen; on non-RT it can happen when\n     softirq processing is deferred to ksoftirqd)\n  3. mvneta_stop_dev =\u003e napi_disable(): cancels the pending poll\n     without executing the completion path\n  4. suspend_device_irqs =\u003e IRQCHIP_MASK_ON_SUSPEND: masks MPIC\n     (already masked, but records IRQS_SUSPENDED)\n  5. Resume: mpic_resume checks irq_percpu_is_enabled() =\u003e false\n     (bit was cleared in step 1) =\u003e skips unmask\n  6. mvneta_start_dev only restores device-level INTR_NEW_MASK,\n     does not touch the MPIC per-CPU mask\n\nResult: MPIC per-CPU interrupt stays masked permanently. The NIC\ngenerates interrupts (INTR_NEW_CAUSE != 0) but the CPU never\nreceives them, causing complete loss of network connectivity.\n\nFix by calling on_each_cpu(mvneta_percpu_enable) in the resume path\nto unconditionally unmask the MPIC per-CPU interrupt regardless of\npre-suspend state.",
  "id": "GHSA-xrfh-4hq6-c36g",
  "modified": "2026-08-17T06:33:28Z",
  "published": "2026-08-15T06:32:23Z",
  "references": [
    {
      "type": "ADVISORY",
      "url": "https://nvd.nist.gov/vuln/detail/CVE-2026-72409"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/1cc312dc8bc78fa24c80d5bc193dbf5b57a99cc6"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/5bdb33ff6e58bdc43632e98b30723eb65352d671"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/82c13027ed283b856017adee970dbfdffce5c6b8"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/8c7a489aa71d2693752b2e794a68bf672d16c829"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/b84dd48f9da1eb132bdc06a944423cd5a1641ef1"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/be626ac1faadd49c2cead9f9cd06ba8752d81563"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/bf88cd3b649bc3e638f1e8a77649581852747a68"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/fd398d6480987e4c84fff0aaab6b9d6642a93343"
    }
  ],
  "schema_version": "1.4.0",
  "severity": [
    {
      "score": "CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:H",
      "type": "CVSS_V3"
    }
  ]
}



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