GHSA-95J3-7Q26-W637

Vulnerability from github – Published: 2026-07-19 18:31 – Updated: 2026-07-20 15:31
VLAI
Details

In the Linux kernel, the following vulnerability has been resolved:

octeontx2-af: validate body pcifunc in rvu_mbox_handler_rep_event_notify

rvu_mbox_handler_rep_event_notify() in drivers/net/ethernet/marvell/ octeontx2/af/rvu_rep.c queues a sender-controlled REP_EVENT_NOTIFY request body verbatim, and rvu_rep_up_notify() then forwards event->pcifunc (the nested body field, distinct from the AF-normalised header pcifunc) into rvu_get_pfvf(), rvu_get_pf() and the AF->PF mailbox device index without any bounds check.

A VF attached to a PF that has been put into switchdev representor mode reaches this path: the VF mailbox handler otx2_pfvf_mbox_handler() forwards every message id including MBOX_MSG_REP_EVENT_NOTIFY to AF without an allowlist, and the AF dispatcher rewrites only msg->pcifunc, leaving struct rep_event::pcifunc attacker-controlled. The sibling rvu_mbox_handler_esw_cfg() refuses requests whose header pcifunc is not rvu->rep_pcifunc; this handler has no equivalent gate.

An out-of-range body pcifunc selects an &rvu->pf[]/&rvu->hwvf[] element past the allocated array and, for RVU_EVENT_MAC_ADDR_CHANGE, turns into a six-byte attacker-chosen OOB ether_addr_copy() target inside the queued worker; KASAN reports a slab-out-of-bounds write in rvu_rep_wq_handler.

Reject malformed requests at the handler entry by gating on is_pf_func_valid(), which is already the canonical PF/VF range check in this driver; expose it via rvu.h so callers in rvu_rep.c can use it instead of open-coding the same range arithmetic.

Show details on source website

{
  "affected": [],
  "aliases": [
    "CVE-2026-63923"
  ],
  "database_specific": {
    "cwe_ids": [],
    "github_reviewed": false,
    "github_reviewed_at": null,
    "nvd_published_at": "2026-07-19T16:17:10Z",
    "severity": "HIGH"
  },
  "details": "In the Linux kernel, the following vulnerability has been resolved:\n\nocteontx2-af: validate body pcifunc in rvu_mbox_handler_rep_event_notify\n\nrvu_mbox_handler_rep_event_notify() in drivers/net/ethernet/marvell/\nocteontx2/af/rvu_rep.c queues a sender-controlled REP_EVENT_NOTIFY\nrequest body verbatim, and rvu_rep_up_notify() then forwards\nevent-\u003epcifunc (the nested body field, distinct from the\nAF-normalised header pcifunc) into rvu_get_pfvf(), rvu_get_pf() and\nthe AF-\u003ePF mailbox device index without any bounds check.\n\nA VF attached to a PF that has been put into switchdev\nrepresentor mode reaches this path: the VF mailbox handler\notx2_pfvf_mbox_handler() forwards every message id including\nMBOX_MSG_REP_EVENT_NOTIFY to AF without an allowlist, and the AF\ndispatcher rewrites only msg-\u003epcifunc, leaving struct\nrep_event::pcifunc attacker-controlled.  The sibling\nrvu_mbox_handler_esw_cfg() refuses requests whose header pcifunc\nis not rvu-\u003erep_pcifunc; this handler has no equivalent gate.\n\nAn out-of-range body pcifunc selects an \u0026rvu-\u003epf[]/\u0026rvu-\u003ehwvf[]\nelement past the allocated array and, for RVU_EVENT_MAC_ADDR_CHANGE,\nturns into a six-byte attacker-chosen OOB ether_addr_copy() target\ninside the queued worker; KASAN reports a slab-out-of-bounds write\nin rvu_rep_wq_handler.\n\nReject malformed requests at the handler entry by gating on\nis_pf_func_valid(), which is already the canonical PF/VF range check\nin this driver; expose it via rvu.h so callers in rvu_rep.c can use\nit instead of open-coding the same range arithmetic.",
  "id": "GHSA-95j3-7q26-w637",
  "modified": "2026-07-20T15:31:51Z",
  "published": "2026-07-19T18:31:46Z",
  "references": [
    {
      "type": "ADVISORY",
      "url": "https://nvd.nist.gov/vuln/detail/CVE-2026-63923"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/2156a29aecfffa2eb7c558255690084efbe9f3b0"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/68be0260e2a02ff9b18a8678d5f8d1715fa20138"
    }
  ],
  "schema_version": "1.4.0",
  "severity": [
    {
      "score": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H",
      "type": "CVSS_V3"
    }
  ]
}



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