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CVE-2025-37964 (GCVE-0-2025-37964)

Vulnerability from cvelistv5 – Published: 2025-05-20 16:01 – Updated: 2026-09-08 08:41
VLAI
Title
x86/mm: Eliminate window where TLB flushes may be inadvertently skipped
Summary
In the Linux kernel, the following vulnerability has been resolved: x86/mm: Eliminate window where TLB flushes may be inadvertently skipped tl;dr: There is a window in the mm switching code where the new CR3 is set and the CPU should be getting TLB flushes for the new mm. But should_flush_tlb() has a bug and suppresses the flush. Fix it by widening the window where should_flush_tlb() sends an IPI. Long Version: === History === There were a few things leading up to this. First, updating mm_cpumask() was observed to be too expensive, so it was made lazier. But being lazy caused too many unnecessary IPIs to CPUs due to the now-lazy mm_cpumask(). So code was added to cull mm_cpumask() periodically[2]. But that culling was a bit too aggressive and skipped sending TLB flushes to CPUs that need them. So here we are again. === Problem === The too-aggressive code in should_flush_tlb() strikes in this window: // Turn on IPIs for this CPU/mm combination, but only // if should_flush_tlb() agrees: cpumask_set_cpu(cpu, mm_cpumask(next)); next_tlb_gen = atomic64_read(&next->context.tlb_gen); choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush); load_new_mm_cr3(need_flush); // ^ After 'need_flush' is set to false, IPIs *MUST* // be sent to this CPU and not be ignored. this_cpu_write(cpu_tlbstate.loaded_mm, next); // ^ Not until this point does should_flush_tlb() // become true! should_flush_tlb() will suppress TLB flushes between load_new_mm_cr3() and writing to 'loaded_mm', which is a window where they should not be suppressed. Whoops. === Solution === Thankfully, the fuzzy "just about to write CR3" window is already marked with loaded_mm==LOADED_MM_SWITCHING. Simply checking for that state in should_flush_tlb() is sufficient to ensure that the CPU is targeted with an IPI. This will cause more TLB flush IPIs. But the window is relatively small and I do not expect this to cause any kind of measurable performance impact. Update the comment where LOADED_MM_SWITCHING is written since it grew yet another user. Peter Z also raised a concern that should_flush_tlb() might not observe 'loaded_mm' and 'is_lazy' in the same order that switch_mm_irqs_off() writes them. Add a barrier to ensure that they are observed in the order they are written.
Severity
7.8 (High)
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H
Assigner
References
Impacted products
Vendor Product Version CPE status
Linux Linux Affected: 848b5815177582de0e1d0118725378e0fbadca20 , < 12f703811af043d32b1c8a30001b2fa04d5cd0ac (git)
Affected: b47002ed65ade940839b7f439ff4a194e7d5ec28 , < 02ad4ce144bd27f71f583f667fdf3b3ba0753477 (git)
Affected: a04fe3bfc71e28009e20357b79df1e8ef7c9d600 , < d41072906abec8bb8e01ed16afefbaa558908c89 (git)
Affected: 3dbe889a1b829b4c07e0836ff853fe649e51ce4f , < d87392094f96e162fa5fa5a8640d70cc0952806f (git)
Affected: 6db2526c1d694c91c6e05e2f186c085e9460f202 , < 399ec9ca8fc4999e676ff89a90184ec40031cf59 (git)
Affected: 6db2526c1d694c91c6e05e2f186c085e9460f202 , < fea4e317f9e7e1f449ce90dedc27a2d2a95bee5a (git)
Affected: d1347977661342cb09a304a17701eb2d4aa21dec (git)
Affected: 5.15.179 , < 5.15.183 (semver)
Affected: 6.1.129 , < 6.1.139 (semver)
Affected: 6.6.79 , < 6.6.91 (semver)
Affected: 6.12.16 , < 6.12.29 (semver)
Affected: 6.13.4 , < 6.14 (semver)
guessed Create a notification for this product.
Linux Linux Affected: 6.14
Unaffected: 0 , < 6.14 (semver)
Unaffected: 5.15.183 , ≤ 5.15.* (semver)
Unaffected: 6.1.139 , ≤ 6.1.* (semver)
Unaffected: 6.6.91 , ≤ 6.6.* (semver)
Unaffected: 6.12.29 , ≤ 6.12.* (semver)
Unaffected: 6.14.7 , ≤ 6.14.* (semver)
Unaffected: 6.15 , ≤ * (original_commit_for_fix)
guessed Create a notification for this product.
Siemens SIMATIC S7-1500 CPU 1518-4 PN/DP MFP Affected: V3.1.6 , < * (custom)
guessed Create a notification for this product.
Siemens SIMATIC S7-1500 CPU 1518F-4 PN/DP MFP Affected: V3.1.6 , < * (custom)
guessed Create a notification for this product.
Siemens SIPLUS S7-1500 CPU 1518-4 PN/DP MFP Affected: V3.1.6 , < * (custom)
guessed Create a notification for this product.
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            "lang": "en",
            "value": "In the Linux kernel, the following vulnerability has been resolved:\n\nx86/mm: Eliminate window where TLB flushes may be inadvertently skipped\n\ntl;dr: There is a window in the mm switching code where the new CR3 is\nset and the CPU should be getting TLB flushes for the new mm.  But\nshould_flush_tlb() has a bug and suppresses the flush.  Fix it by\nwidening the window where should_flush_tlb() sends an IPI.\n\nLong Version:\n\n=== History ===\n\nThere were a few things leading up to this.\n\nFirst, updating mm_cpumask() was observed to be too expensive, so it was\nmade lazier.  But being lazy caused too many unnecessary IPIs to CPUs\ndue to the now-lazy mm_cpumask().  So code was added to cull\nmm_cpumask() periodically[2].  But that culling was a bit too aggressive\nand skipped sending TLB flushes to CPUs that need them.  So here we are\nagain.\n\n=== Problem ===\n\nThe too-aggressive code in should_flush_tlb() strikes in this window:\n\n\t// Turn on IPIs for this CPU/mm combination, but only\n\t// if should_flush_tlb() agrees:\n\tcpumask_set_cpu(cpu, mm_cpumask(next));\n\n\tnext_tlb_gen = atomic64_read(\u0026next-\u003econtext.tlb_gen);\n\tchoose_new_asid(next, next_tlb_gen, \u0026new_asid, \u0026need_flush);\n\tload_new_mm_cr3(need_flush);\n\t// ^ After \u0027need_flush\u0027 is set to false, IPIs *MUST*\n\t// be sent to this CPU and not be ignored.\n\n        this_cpu_write(cpu_tlbstate.loaded_mm, next);\n\t// ^ Not until this point does should_flush_tlb()\n\t// become true!\n\nshould_flush_tlb() will suppress TLB flushes between load_new_mm_cr3()\nand writing to \u0027loaded_mm\u0027, which is a window where they should not be\nsuppressed.  Whoops.\n\n=== Solution ===\n\nThankfully, the fuzzy \"just about to write CR3\" window is already marked\nwith loaded_mm==LOADED_MM_SWITCHING.  Simply checking for that state in\nshould_flush_tlb() is sufficient to ensure that the CPU is targeted with\nan IPI.\n\nThis will cause more TLB flush IPIs.  But the window is relatively small\nand I do not expect this to cause any kind of measurable performance\nimpact.\n\nUpdate the comment where LOADED_MM_SWITCHING is written since it grew\nyet another user.\n\nPeter Z also raised a concern that should_flush_tlb() might not observe\n\u0027loaded_mm\u0027 and \u0027is_lazy\u0027 in the same order that switch_mm_irqs_off()\nwrites them.  Add a barrier to ensure that they are observed in the\norder they are written."
          },
          {
            "lang": "es",
            "value": "En el kernel de Linux, se ha resuelto la siguiente vulnerabilidad: x86/mm: Eliminar la ventana donde los vaciados de TLB pueden omitirse inadvertidamente tl;dr: Hay una ventana en el c\u00f3digo de conmutaci\u00f3n mm donde se establece el nuevo CR3 y la CPU deber\u00eda obtener vaciados de TLB para el nuevo mm. Pero should_flush_tlb() tiene un error y suprime el vaciado. Arr\u00e9glelo ampliando la ventana donde should_flush_tlb() env\u00eda una IPI. Versi\u00f3n larga: === Historial === Hubo algunas cosas que llevaron a esto. Primero, se observ\u00f3 que actualizar mm_cpumask() era demasiado costoso, por lo que se hizo m\u00e1s perezoso. Pero ser perezoso caus\u00f3 demasiados IPI innecesarios a las CPU debido al ahora perezoso mm_cpumask(). Entonces se agreg\u00f3 c\u00f3digo para descartar mm_cpumask() peri\u00f3dicamente[2]. Pero ese descarte fue demasiado agresivo y omiti\u00f3 el env\u00edo de vaciados de TLB a las CPU que los necesitan. As\u00ed que aqu\u00ed estamos de nuevo. === Problema === El c\u00f3digo demasiado agresivo en should_flush_tlb() ataca en esta ventana: // Activa las IPI para esta combinaci\u00f3n de CPU/mm, pero solo si should_flush_tlb() est\u00e1 de acuerdo: cpumask_set_cpu(cpu, mm_cpumask(next)); next_tlb_gen = atomic64_read(\u0026amp;next-\u0026gt;context.tlb_gen); choose_new_asid(next, next_tlb_gen, \u0026amp;new_asid, \u0026amp;need_flush); load_new_mm_cr3(need_flush); // ^ Despu\u00e9s de que \u0027need_flush\u0027 se establece en falso, las IPI *DEBEN* // enviarse a esta CPU y no ignorarse. this_cpu_write(cpu_tlbstate.loaded_mm, next); // ^ \u00a1No es hasta este punto que should_flush_tlb() // se vuelve verdadero! should_flush_tlb() suprimir\u00e1 los vaciados de TLB entre load_new_mm_cr3() y la escritura en \u0027loaded_mm\u0027, que es una ventana donde no deber\u00edan suprimirse. \u00a1Uy! === Soluci\u00f3n === Afortunadamente, la ventana difusa \"a punto de escribir CR3\" ya est\u00e1 marcada con load_mm==LOADED_MM_SWITCHING. Simplemente comprobar ese estado en should_flush_tlb() es suficiente para asegurar que la CPU est\u00e9 dirigida a un IPI. Esto provocar\u00e1 m\u00e1s IPI de vaciado de TLB. Sin embargo, la ventana es relativamente peque\u00f1a y no preveo que esto tenga ning\u00fan impacto medible en el rendimiento. Actualice el comentario donde se escribe LOADED_MM_SWITCHING, ya que ha generado otro usuario. Peter Z tambi\u00e9n plante\u00f3 la preocupaci\u00f3n de que should_flush_tlb() podr\u00eda no observar \u0027loaded_mm\u0027 e \u0027is_lazy\u0027 en el mismo orden en que switch_mm_irqs_off() los escribe. A\u00f1ade una barrera para garantizar que se observen en el orden en que est\u00e1n escritos."
          }
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        "id": "CVE-2025-37964",
        "lastModified": "2026-07-30T06:22:39.317",
        "metrics": {
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                "attackVector": "LOCAL",
                "availabilityImpact": "HIGH",
                "baseScore": 7.8,
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                "confidentialityImpact": "HIGH",
                "integrityImpact": "HIGH",
                "privilegesRequired": "LOW",
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                "integrityImpact": "NONE",
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              "source": "nvd@nist.gov",
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        "sourceIdentifier": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
        "vulnStatus": "Modified",
        "weaknesses": [
          {
            "description": [
              {
                "lang": "en",
                "value": "NVD-CWE-noinfo"
              }
            ],
            "source": "nvd@nist.gov",
            "type": "Primary"
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    },
    "redhat_vex": {
      "aggregate_severity": "Moderate",
      "current_release_date": "2026-07-30T09:17:52+00:00",
      "cve": "CVE-2025-37964",
      "id": "CVE-2025-37964",
      "initial_release_date": "2025-05-20T00:00:00+00:00",
      "product_status:known_affected": "42",
      "product_status:known_not_affected": "232",
      "source": "Red Hat CSAF VEX",
      "status": "final",
      "title": "kernel: x86/mm: Eliminate window where TLB flushes may be inadvertently skipped",
      "url": "https://security.access.redhat.com/data/csaf/v2/vex/2025/cve-2025-37964.json",
      "version": "3"
    }
  }
}



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Forecast uses a logistic model when the trend is rising, or an exponential decay model when the trend is falling. Fitted via linearized least squares.

Sightings

Author Source Type Date Other

Nomenclature

  • Seen: The vulnerability was mentioned, discussed, or observed by the user.
  • Confirmed: The vulnerability has been validated from an analyst's perspective.
  • Published Proof of Concept: A public proof of concept is available for this vulnerability.
  • Exploited: The vulnerability was observed as exploited by the user who reported the sighting.
  • Patched: The vulnerability was observed as successfully patched by the user who reported the sighting.
  • Not exploited: The vulnerability was not observed as exploited by the user who reported the sighting.
  • Not confirmed: The user expressed doubt about the validity of the vulnerability.
  • Not patched: The vulnerability was not observed as successfully patched by the user who reported the sighting.


Detection rules are retrieved from Rulezet.


Related by attack behaviour

Vulnerabilities whose description is nearest to this one in the vector space of the CIRCL/vulnerability-attack-technique-biencoder model. This is a similarity search over the bi-encoder space (plain cosine), not a classification, and it has no measured accuracy.