{"metadata": {"vulnerability": "CVE-2025-37964", "count": 234, "kinds": {"milestone": 44, "sighting": 2, "kev": 0, "other": 188}}, "data": [{"timestamp": "2025-04-16T04:51:23.974Z", "date_only": false, "value": "2025-04-16T04:51:23.974Z", "kind": "milestone", "label": "Reserved", "source": "cvelistv5", "record": "CVE-2025-37964", "field": "cveMetadata.dateReserved"}, {"timestamp": "2025-05-20T16:01:56.013Z", "date_only": false, "value": "2025-05-20T16:01:56.013Z", "kind": "milestone", "label": "Published", "source": "cvelistv5", "record": "CVE-2025-37964", "field": "cveMetadata.datePublished"}, {"timestamp": "2025-05-20T16:15:00Z", "date_only": false, "value": "2025-05-20T16:15:00Z", "kind": "milestone", "label": "Published", "source": "osv_ubuntu \u00b7 UBUNTU-CVE-2025-37964", "record": "UBUNTU-CVE-2025-37964", "field": "published"}, {"timestamp": "2025-05-20T16:15:34Z", "date_only": false, "value": "2025-05-20T16:15:34Z", "kind": "other", "label": "Nvd published at", "source": "github \u00b7 GHSA-XXW2-VX44-7CV6", "record": "GHSA-XXW2-VX44-7CV6", "field": "database_specific.nvd_published_at"}, {"timestamp": "2025-05-20T16:15:34.683Z", "date_only": false, "value": "2025-05-20T16:15:34.683", "kind": "milestone", "label": "Published", "source": "fkie_nvd \u00b7 FKIE_CVE-2025-37964", "record": "FKIE_CVE-2025-37964", "field": "published"}, {"timestamp": "2025-05-20T16:41:12Z", "date_only": false, "value": "2025-05-20T16:41:12.000000Z", "kind": "sighting", "label": "Published proof of concept", "source": "https://t.me/DarkWebInformer_CVEAlerts/17019", "record": "CVE-2025-37964", "field": "creation_timestamp", "uuid": "8ffba2ed-fb0c-4a2f-933f-6e83815964e4", "content": "\ud83d\udd17 DarkWebInformer.com - Cyber Threat Intelligence\n\ud83d\udccc CVE ID: CVE-2025-37964\n\ud83d\udd25 CVSS Score: N/A\n\ud83d\udd39 Description: In the Linux kernel, the following vulnerability has been resolved:\n\nx86/mm: Eliminate window where TLB flushes may be inadvertently skipped\n\ntl;dr: There is a window in the mm switching code where the new CR3 is\nset and the CPU should be getting TLB flushes for the new mm.  But\nshould_flush_tlb() has a bug and suppresses the flush.  Fix it by\nwidening the window where should_flush_tlb() sends an IPI.\n\nLong Version:\n\n=== History ===\n\nThere were a few things leading up to this.\n\nFirst, updating mm_cpumask() was observed to be too expensive, so it was\nmade lazier.  But being lazy caused too many unnecessary IPIs to CPUs\ndue to the now-lazy mm_cpumask().  So code was added to cull\nmm_cpumask() periodically[2].  But that culling was a bit too aggressive\nand skipped sending TLB flushes to CPUs that need them.  So here we are\nagain.\n\n=== Problem ===\n\nThe too-aggressive code in should_flush_tlb() strikes in this window:\n\n // Turn on IPIs for this CPU/mm combination, but only\n // if should_flush_tlb() agrees:\n cpumask_set_cpu(cpu, mm_cpumask(next));\n\n next_tlb_gen = atomic64_read(&next->context.tlb_gen);\n choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush);\n load_new_mm_cr3(need_flush);\n // ^ After 'need_flush' is set to false, IPIs *MUST*\n // be sent to this CPU and not be ignored.\n\n        this_cpu_write(cpu_tlbstate.loaded_mm, next);\n // ^ Not until this point does should_flush_tlb()\n // become true!\n\nshould_flush_tlb() will suppress TLB flushes between load_new_mm_cr3()\nand writing to 'loaded_mm', which is a window where they should not be\nsuppressed.  Whoops.\n\n=== Solution ===\n\nThankfully, the fuzzy \"just about to write CR3\" window is already marked\nwith loaded_mm==LOADED_MM_SWITCHING.  Simply checking for that state in\nshould_flush_tlb() is sufficient to ensure that the CPU is targeted with\nan IPI.\n\nThis will cause more TLB flush IPIs.  But the window is relatively small\nand I do not expect this to cause any kind of measurable performance\nimpact.\n\nUpdate the comment where LOADED_MM_SWITCHING is written since it grew\nyet another user.\n\nPeter Z also raised a concern that should_flush_tlb() might not observe\n'loaded_mm' and 'is_lazy' in the same order that switch_mm_irqs_off()\nwrites them.  Add a barrier to ensure that they are observed in the\norder they are written.\n\ud83d\udccf Published: 2025-05-20T16:01:56.013Z\n\ud83d\udccf Modified: 2025-05-20T16:01:56.013Z\n\ud83d\udd17 References:\n1. https://git.kernel.org/stable/c/12f703811af043d32b1c8a30001b2fa04d5cd0ac\n2. https://git.kernel.org/stable/c/02ad4ce144bd27f71f583f667fdf3b3ba0753477\n3. https://git.kernel.org/stable/c/d41072906abec8bb8e01ed16afefbaa558908c89\n4. https://git.kernel.org/stable/c/d87392094f96e162fa5fa5a8640d70cc0952806f\n5. https://git.kernel.org/stable/c/399ec9ca8fc4999e676ff89a90184ec40031cf59\n6. https://git.kernel.org/stable/c/fea4e317f9e7e1f449ce90dedc27a2d2a95bee5a", "url": "https://t.me/DarkWebInformer_CVEAlerts/17019"}, {"timestamp": "2025-05-20T18:30:57Z", "date_only": false, "value": "2025-05-20T18:30:57Z", "kind": "milestone", "label": "Published", "source": "github \u00b7 GHSA-XXW2-VX44-7CV6", "record": "GHSA-XXW2-VX44-7CV6", "field": "published"}, {"timestamp": "2025-05-20T22:00:00Z", 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