GHSA-R5W5-QJWH-6PQ3
Vulnerability from github – Published: 2026-10-18 18:31 – Updated: 2026-10-18 18:31In the Linux kernel, the following vulnerability has been resolved:
perf/core: Fill branch entries with a single assignment
perf_clear_branch_entry_bitfields() clears the bitfields of struct perf_branch_entry one by one and leaves from/to alone, since callers overwrite those straight away. The list has to be kept in sync with the struct by hand and has already fallen behind: new_type and priv were added to perf_branch_entry and never added here.
Only BRBE writes those two, and neither for every record. brbe_set_perf_entry_type() leaves new_type alone for a branch type it does not recognise, and priv is not set for source-only records. arm_pmuv3.c allocates the per-CPU branch stack with kmalloc(), so such a record reaches userspace with whatever the slot held: uninitialised kmalloc() data on the first pass over the buffer, the previous record's values after that. Nothing under arch/x86/events/ writes either field, so only arm64 is affected.
Assign the whole entry at each site instead. Everything not named is then zero, and there is no list to keep in sync. The bitfields add up to exactly 64 bits, so the struct has no padding to leave undefined.
perf_clear_branch_entry_bitfields() has no callers left, so remove it. perf_entry_from_brbe_regset() assigns an empty literal instead, since it fills from/to conditionally. PERF_BR_SPEC_NA is 0, so dropping the explicit spec assignment changes nothing.
{
"affected": [],
"aliases": [
"CVE-2026-98551"
],
"database_specific": {
"cwe_ids": [],
"github_reviewed": false,
"github_reviewed_at": null,
"nvd_published_at": "2026-10-18T16:17:07Z",
"severity": null
},
"details": "In the Linux kernel, the following vulnerability has been resolved:\n\nperf/core: Fill branch entries with a single assignment\n\nperf_clear_branch_entry_bitfields() clears the bitfields of struct\nperf_branch_entry one by one and leaves from/to alone, since callers\noverwrite those straight away. The list has to be kept in sync with the\nstruct by hand and has already fallen behind: new_type and priv were\nadded to perf_branch_entry and never added here.\n\nOnly BRBE writes those two, and neither for every record.\nbrbe_set_perf_entry_type() leaves new_type alone for a branch type it\ndoes not recognise, and priv is not set for source-only records.\narm_pmuv3.c allocates the per-CPU branch stack with kmalloc(), so such a\nrecord reaches userspace with whatever the slot held: uninitialised\nkmalloc() data on the first pass over the buffer, the previous record\u0027s\nvalues after that. Nothing under arch/x86/events/ writes either field,\nso only arm64 is affected.\n\nAssign the whole entry at each site instead. Everything not named is\nthen zero, and there is no list to keep in sync. The bitfields add up to\nexactly 64 bits, so the struct has no padding to leave undefined.\n\nperf_clear_branch_entry_bitfields() has no callers left, so remove it.\nperf_entry_from_brbe_regset() assigns an empty literal instead, since it\nfills from/to conditionally. PERF_BR_SPEC_NA is 0, so dropping the\nexplicit spec assignment changes nothing.",
"id": "GHSA-r5w5-qjwh-6pq3",
"modified": "2026-10-18T18:31:54Z",
"published": "2026-10-18T18:31:54Z",
"references": [
{
"type": "ADVISORY",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2026-98551"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/24b620729e53d978b3e425f55bc66efd3bab1f59"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/c7de8521947a521b766979ff5c09f66fe905a5bd"
}
],
"schema_version": "1.4.0",
"severity": []
}
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