GHSA-H7VJ-5R6R-3R99
Vulnerability from github – Published: 2026-09-17 18:31 – Updated: 2026-09-18 18:31In the Linux kernel, the following vulnerability has been resolved:
iommu/vt-d: Clear Present bit before tearing down copied context entry
copied_context_tear_down() zeroes the 128-bit context entry with context_clear_entry() while the Present bit is still set, and only then issues the context-cache and IOTLB invalidations. This leaves a window in which hardware can fetch a torn entry, with some fields already zeroed while Present is still set, leading to unpredictable behaviour or spurious faults. While x86 provides strong write ordering, the compiler may reorder the writes to the two 64-bit halves of the entry, and the hardware fetch is not guaranteed to be atomic with respect to multiple CPU writes.
There is no cacheline flush before the invalidation either, so on an IOMMU without coherent access to the context table the zeroed entry may not be visible to hardware at the point the invalidation is submitted.
Apply the same ownership handshake described in the VT-d spec, Section 6.5.3.3 ("Guidance to Software for Invalidations"): clear only the Present bit, flush it out to the IOMMU, perform the invalidations, and only then zero the remainder of the entry.
{
"affected": [],
"aliases": [
"CVE-2026-90243"
],
"database_specific": {
"cwe_ids": [],
"github_reviewed": false,
"github_reviewed_at": null,
"nvd_published_at": "2026-09-17T17:17:20Z",
"severity": "HIGH"
},
"details": "In the Linux kernel, the following vulnerability has been resolved:\n\niommu/vt-d: Clear Present bit before tearing down copied context entry\n\ncopied_context_tear_down() zeroes the 128-bit context entry with\ncontext_clear_entry() while the Present bit is still set, and only then\nissues the context-cache and IOTLB invalidations. This leaves a window\nin which hardware can fetch a torn entry, with some fields already zeroed\nwhile Present is still set, leading to unpredictable behaviour or\nspurious faults. While x86 provides strong write ordering, the compiler\nmay reorder the writes to the two 64-bit halves of the entry, and the\nhardware fetch is not guaranteed to be atomic with respect to multiple\nCPU writes.\n\nThere is no cacheline flush before the invalidation either, so on an\nIOMMU without coherent access to the context table the zeroed entry may\nnot be visible to hardware at the point the invalidation is submitted.\n\nApply the same ownership handshake described in the VT-d spec, Section\n6.5.3.3 (\"Guidance to Software for Invalidations\"): clear only the Present\nbit, flush it out to the IOMMU, perform the invalidations, and only then\nzero the remainder of the entry.",
"id": "GHSA-h7vj-5r6r-3r99",
"modified": "2026-09-18T18:31:28Z",
"published": "2026-09-17T18:31:57Z",
"references": [
{
"type": "ADVISORY",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2026-90243"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/3c88cfedc7768b1ae2dc7ddc71547ae9a1aaff7d"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/6b822d18c33af9d1e16a8e5e6aa6e656987b09de"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/97750a8dce79c1a9b2b2d2a020b61b800141996c"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/f532c57985b1a7d6b7e37e05506b46d413e5cca4"
}
],
"schema_version": "1.4.0",
"severity": [
{
"score": "CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:H/I:H/A:H",
"type": "CVSS_V3"
}
]
}
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