Vulnerability-Lookup

GHSA-G2MQ-V2G4-XGCX

Vulnerability from github – Published: 2024-08-17 09:30 – Updated: 2025-10-02 21:31

Details

In the Linux kernel, the following vulnerability has been resolved:

spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.

Severity

5.5 (Medium)


                  
                    CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H

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{
  "affected": [],
  "aliases": [
    "CVE-2024-42279"
  ],
  "database_specific": {
    "cwe_ids": [],
    "github_reviewed": false,
    "github_reviewed_at": null,
    "nvd_published_at": "2024-08-17T09:15:08Z",
    "severity": "MODERATE"
  },
  "details": "In the Linux kernel, the following vulnerability has been resolved:\n\nspi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer\n\nWhile transmitting with rx_len == 0, the RX FIFO is not going to be\nemptied in the interrupt handler. A subsequent transfer could then\nread crap from the previous transfer out of the RX FIFO into the\nstart RX buffer. The core provides a register that will empty the RX and\nTX FIFOs, so do that before each transfer.",
  "id": "GHSA-g2mq-v2g4-xgcx",
  "modified": "2025-10-02T21:31:03Z",
  "published": "2024-08-17T09:30:24Z",
  "references": [
    {
      "type": "ADVISORY",
      "url": "https://nvd.nist.gov/vuln/detail/CVE-2024-42279"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/3feda3677e8bbe833c3a62a4091377a08f015b80"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/45e03d35229b680b79dfea1103a1f2f07d0b5d75"
    },
    {
      "type": "WEB",
      "url": "https://git.kernel.org/stable/c/9cf71eb0faef4bff01df4264841b8465382d7927"
    }
  ],
  "schema_version": "1.4.0",
  "severity": [
    {
      "score": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H",
      "type": "CVSS_V3"
    }
  ]
}

CVE-2024-42279 (GCVE-0-2024-42279)

Vulnerability from cvelistv5 – Published: 2024-08-17 09:08 – Updated: 2026-08-05 11:36

Title

spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

Summary

In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.

Severity

7.8 (High)


                        
                          CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H

SSVC

Exploitation: none Automatable: no Technical Impact: partial

CISA Coordinator · CISA-ADP (v2.0.3)

Decision recorded 2024-09-10 16:11 UTC

Assigner

Linux CNA under the mitre root

CNA scorecard D 53/100 over 6667 records in the last 180 days details

References

3 references

URL	Tags
https://git.kernel.org/stable/c/3feda3677e8bbe833…
https://git.kernel.org/stable/c/45e03d35229b680b7…
https://git.kernel.org/stable/c/9cf71eb0faef4bff0…

Impacted products

2 products

Vendor	Product	Version
Linux	Linux	Affected: 9ac8d17694b66d54b13e9718b25c14ca36dbebbd , < 3feda3677e8bbe833c3a62a4091377a08f015b80 (git) Affected: 9ac8d17694b66d54b13e9718b25c14ca36dbebbd , < 45e03d35229b680b79dfea1103a1f2f07d0b5d75 (git) Affected: 9ac8d17694b66d54b13e9718b25c14ca36dbebbd , < 9cf71eb0faef4bff01df4264841b8465382d7927 (git)
Linux	Linux	Affected: 6.0 Unaffected: 0 , < 6.0 (semver) Unaffected: 6.6.44 , ≤ 6.6.* (semver) Unaffected: 6.10.3 , ≤ 6.10.* (semver) Unaffected: 6.11 , ≤ * (original_commit_for_fix)

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  "containers": {
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      {
        "metrics": [
          {
            "other": {
              "content": {
                "id": "CVE-2024-42279",
                "options": [
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                  },
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                    "Automatable": "no"
                  },
                  {
                    "Technical Impact": "partial"
                  }
                ],
                "role": "CISA Coordinator",
                "timestamp": "2024-09-10T16:11:42.802690Z",
                "version": "2.0.3"
              },
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        "providerMetadata": {
          "dateUpdated": "2024-09-12T17:33:31.191Z",
          "orgId": "134c704f-9b21-4f2e-91b3-4a467353bcc0",
          "shortName": "CISA-ADP"
        },
        "title": "CISA ADP Vulnrichment"
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    ],
    "cna": {
      "affected": [
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          "defaultStatus": "unaffected",
          "product": "Linux",
          "programFiles": [
            "drivers/spi/spi-microchip-core.c"
          ],
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          "vendor": "Linux",
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              "versionType": "git"
            },
            {
              "lessThan": "45e03d35229b680b79dfea1103a1f2f07d0b5d75",
              "status": "affected",
              "version": "9ac8d17694b66d54b13e9718b25c14ca36dbebbd",
              "versionType": "git"
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            {
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              "status": "affected",
              "version": "9ac8d17694b66d54b13e9718b25c14ca36dbebbd",
              "versionType": "git"
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        },
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          "defaultStatus": "affected",
          "product": "Linux",
          "programFiles": [
            "drivers/spi/spi-microchip-core.c"
          ],
          "repo": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
          "vendor": "Linux",
          "versions": [
            {
              "status": "affected",
              "version": "6.0"
            },
            {
              "lessThan": "6.0",
              "status": "unaffected",
              "version": "0",
              "versionType": "semver"
            },
            {
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              "status": "unaffected",
              "version": "6.6.44",
              "versionType": "semver"
            },
            {
              "lessThanOrEqual": "6.10.*",
              "status": "unaffected",
              "version": "6.10.3",
              "versionType": "semver"
            },
            {
              "lessThanOrEqual": "*",
              "status": "unaffected",
              "version": "6.11",
              "versionType": "original_commit_for_fix"
            }
          ]
        }
      ],
      "cpeApplicability": [
        {
          "nodes": [
            {
              "cpeMatch": [
                {
                  "criteria": "cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*",
                  "versionEndExcluding": "6.6.44",
                  "versionStartIncluding": "6.0",
                  "vulnerable": true
                },
                {
                  "criteria": "cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*",
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                  "versionStartIncluding": "6.0",
                  "vulnerable": true
                },
                {
                  "criteria": "cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*",
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              "negate": false,
              "operator": "OR"
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      "descriptions": [
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          "lang": "en",
          "value": "In the Linux kernel, the following vulnerability has been resolved:\n\nspi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer\n\nWhile transmitting with rx_len == 0, the RX FIFO is not going to be\nemptied in the interrupt handler. A subsequent transfer could then\nread crap from the previous transfer out of the RX FIFO into the\nstart RX buffer. The core provides a register that will empty the RX and\nTX FIFOs, so do that before each transfer."
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      "metrics": [
        {
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            "baseSeverity": "HIGH",
            "vectorString": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H",
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          },
          "scenarios": [
            {
              "lang": "en",
              "value": "AV:L - The vulnerable `mchp_corespi_transfer_one()` path is entered from the SPI core, reachable locally through spidev ioctls (`SPI_IOC_MESSAGE`) or by driving any in-kernel SPI client; no network or physical access to the board is needed.\nAC:L - The attacker can reliably dirty the RX FIFO with back-to-back transfers (including transfers larger than the 32-byte FIFO that provoke `INT_RX_CHANNEL_OVERFLOW`, or aborted transfers), and the residue is sticky rather than probabilistic, so no condition outside the attacker\u0027s control is required.\nPR:L - Only ordinary local access to an SPI device node (commonly group-accessible on embedded platforms) or the ability to trigger an SPI client is needed; there is no capability check anywhere on the path from the ioctl to `transfer_one`.\nUI:N - The attacker issues the transfers themselves and the stale-FIFO condition persists on its own; no victim action is required.\nS:U - The impact stays within the kernel and the SPI controller managed by it; no VM, IOMMU, or sandbox boundary is crossed.\nC:H - Bytes clocked in during a previous transaction \u2014 from any device on the shared bus, including a TPM, secure element, or the boot/root SPI flash \u2014 are copied into the attacker\u0027s RX buffer, and the leak can be repeated indefinitely, so security-critical data transiting the bus can be siphoned across driver and process boundaries.\nI:H - Residue from the attacker\u0027s own transaction is prepended into the next client\u0027s `rx_buf`, and an attacker transacting with a readback-capable slave controls those bytes exactly, allowing chosen data to be injected into another driver\u0027s input \u2014 e.g. corrupting a secure-element/TPM response or data read from the root flash.\nA:H - The residue count never clears, so once the FIFO fills every subsequent transfer overflows and returns garbage, permanently breaking every device on the controller (rootfs SPI-NOR, watchdog, sensors) until reboot, with SPI core transfer timeouts and `dev_err` spam."
            }
          ]
        }
      ],
      "providerMetadata": {
        "dateUpdated": "2026-08-05T11:36:18.076Z",
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        },
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          "url": "https://git.kernel.org/stable/c/9cf71eb0faef4bff01df4264841b8465382d7927"
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    "datePublished": "2024-08-17T09:08:46.829Z",
    "dateReserved": "2024-07-30T07:40:12.261Z",
    "dateUpdated": "2026-08-05T11:36:18.076Z",
    "state": "PUBLISHED"
  },
  "dataType": "CVE_RECORD",
  "dataVersion": "5.2"
}

Sightings

Author	Source	Type	Date	Other

Nomenclature

Seen: The vulnerability was mentioned, discussed, or observed by the user.
Confirmed: The vulnerability has been validated from an analyst's perspective.
Published Proof of Concept: A public proof of concept is available for this vulnerability.
Exploited: The vulnerability was observed as exploited by the user who reported the sighting.
Patched: The vulnerability was observed as successfully patched by the user who reported the sighting.
Not exploited: The vulnerability was not observed as exploited by the user who reported the sighting.
Not confirmed: The user expressed doubt about the validity of the vulnerability.
Not patched: The vulnerability was not observed as successfully patched by the user who reported the sighting.

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The MITRE ATT&CK techniques below are AI-generated suggestions, inferred from the description of the vulnerability by the CIRCL/vulnerability-attack-technique-classification-roberta-base model, served locally by ML-Gateway. They have not been verified by an analyst and are provided for guidance only.
The approach is described in our paper Mapping CVEs to MITRE ATT&CK Techniques: A Curated Gold-Set Classifier and the Limits of LLM-Assisted Label Expansion.
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