GHSA-C6R3-334M-J754
Vulnerability from github – Published: 2026-10-14 15:32 – Updated: 2026-10-14 15:32In the Linux kernel, the following vulnerability has been resolved:
powerpc/entry: Fix irq_soft_mask corruption on replayed interrupt exit
When __replay_soft_interrupts() replays a pending interrupt (e.g. PACA_IRQ_DEC -> timer_interrupt), it calls the handler directly with a synthetic pt_regs. The DEFINE_INTERRUPT_HANDLER_ASYNC wrapper around each handler calls arch_interrupt_async_exit_prepare() on the way out, which calls arch_interrupt_exit_prepare() -> local_irq_disable() -> arch_local_irq_disable(), which does:
irq_soft_mask_set(IRQS_DISABLED) /* 0x1 */
This unconditionally overwrites irq_soft_mask with IRQS_DISABLED (0x1), stripping the IRQS_PMI_DISABLED (0x2) bit. The result is that irq_soft_mask is 0x1 instead of IRQS_ALL_DISABLED (0x3) when the handler returns to __replay_soft_interrupts().
For a normally-taken interrupt this is harmless: the next interrupt always enters through arch_interrupt_enter_prepare() which unconditionally sets irq_soft_mask to IRQS_ALL_DISABLED. But during replay, next_interrupt() is called directly between replayed handlers without going back through arch_interrupt_enter_prepare(), so the stripped bit is never restored. next_interrupt() then fires a WARNING:
WARNING: arch/powerpc/kernel/irq_64.c:75
WARN_ON(irq_soft_mask_return() != IRQS_ALL_DISABLED)
The warning was observed early in boot on a POWER10 pseries guest during kmem_cache_init_late(), where a spinlock release triggers interrupt replay that processes a pending timer interrupt.
Debugger state confirming the bug: Before timer_interrupt(®s): irq_soft_mask = 0x3 (IRQS_ALL_DISABLED) correct irq_happened = 0x41 (HARD_DIS|REPLAYING) correct After timer_interrupt(®s) returns: irq_soft_mask = 0x1 (IRQS_DISABLED) WRONG - PMI bit stripped irq_happened = 0x41 unchanged
The fix is to replace local_irq_disable() with hard_irq_disable().
hard_irq_disable() is the right primitive here for two reasons:
-
On PPC64 (hw_irq.h:301) it calls irq_soft_mask_set_return(IRQS_ALL_DISABLED), setting the soft mask to 0x3 (both IRQS_DISABLED and IRQS_PMI_DISABLED), which preserves the PMI bit and fixes the WARNING. The additional work it does (__hard_irq_disable(), PACA_IRQ_HARD_DIS |=) is redundant but safe since both are already set at this point in the exit path; the trace_hardirqs_off() inside is guarded by if (!arch_irqs_disabled_flags(flags)) so it will not double-fire.
-
On PPC32 (hw_irq.h:467) hard_irq_disable() maps to arch_local_irq_disable() -> __hard_irq_disable(), which clears MSR[EE] in hardware. This is exactly correct: PPC32 has no soft-mask PACA mechanism, so the hardware disable is the right way to satisfy irqentry_exit()'s requirement. This also fixes a build error on PPC32 where irq_soft_mask_set() is only defined under CONFIG_PPC64:
arch/powerpc/include/asm/entry-common.h:273: error: implicit declaration of function 'irq_soft_mask_set'
Using hard_irq_disable() requires no #ifdef and is consistent with how the rest of the entry code (e.g. entry-common.h:463) handles the same PPC32/PPC64 split.
{
"affected": [],
"aliases": [
"CVE-2026-98395"
],
"database_specific": {
"cwe_ids": [],
"github_reviewed": false,
"github_reviewed_at": null,
"nvd_published_at": "2026-10-14T14:17:50Z",
"severity": null
},
"details": "In the Linux kernel, the following vulnerability has been resolved:\n\npowerpc/entry: Fix irq_soft_mask corruption on replayed interrupt exit\n\nWhen __replay_soft_interrupts() replays a pending interrupt (e.g.\nPACA_IRQ_DEC -\u003e timer_interrupt), it calls the handler directly with a\nsynthetic pt_regs. The DEFINE_INTERRUPT_HANDLER_ASYNC wrapper around\neach handler calls arch_interrupt_async_exit_prepare() on the way out,\nwhich calls arch_interrupt_exit_prepare() -\u003e local_irq_disable() -\u003e\narch_local_irq_disable(), which does:\n\n irq_soft_mask_set(IRQS_DISABLED) /* 0x1 */\n\nThis unconditionally overwrites irq_soft_mask with IRQS_DISABLED (0x1),\nstripping the IRQS_PMI_DISABLED (0x2) bit. The result is that\nirq_soft_mask is 0x1 instead of IRQS_ALL_DISABLED (0x3) when the\nhandler returns to __replay_soft_interrupts().\n\nFor a normally-taken interrupt this is harmless: the next interrupt\nalways enters through arch_interrupt_enter_prepare() which\nunconditionally sets irq_soft_mask to IRQS_ALL_DISABLED. But during\nreplay, next_interrupt() is called directly between replayed handlers\nwithout going back through arch_interrupt_enter_prepare(), so the\nstripped bit is never restored. next_interrupt() then fires a WARNING:\n\n WARNING: arch/powerpc/kernel/irq_64.c:75\n WARN_ON(irq_soft_mask_return() != IRQS_ALL_DISABLED)\n\nThe warning was observed early in boot on a POWER10 pseries guest\nduring kmem_cache_init_late(), where a spinlock release triggers\ninterrupt replay that processes a pending timer interrupt.\n\nDebugger state confirming the bug:\n Before timer_interrupt(\u0026regs):\n irq_soft_mask = 0x3 (IRQS_ALL_DISABLED) correct\n irq_happened = 0x41 (HARD_DIS|REPLAYING) correct\n After timer_interrupt(\u0026regs) returns:\n irq_soft_mask = 0x1 (IRQS_DISABLED) WRONG - PMI bit stripped\n irq_happened = 0x41 unchanged\n\nThe fix is to replace local_irq_disable() with hard_irq_disable().\n\nhard_irq_disable() is the right primitive here for two reasons:\n\n1. On PPC64 (hw_irq.h:301) it calls irq_soft_mask_set_return(IRQS_ALL_DISABLED),\n setting the soft mask to 0x3 (both IRQS_DISABLED and IRQS_PMI_DISABLED),\n which preserves the PMI bit and fixes the WARNING. The additional\n work it does (__hard_irq_disable(), PACA_IRQ_HARD_DIS |=) is\n redundant but safe since both are already set at this point in the\n exit path; the trace_hardirqs_off() inside is guarded by\n if (!arch_irqs_disabled_flags(flags)) so it will not double-fire.\n\n2. On PPC32 (hw_irq.h:467) hard_irq_disable() maps to\n arch_local_irq_disable() -\u003e __hard_irq_disable(), which clears\n MSR[EE] in hardware. This is exactly correct: PPC32 has no soft-mask\n PACA mechanism, so the hardware disable is the right way to satisfy\n irqentry_exit()\u0027s requirement. This also fixes a build error on PPC32\n where irq_soft_mask_set() is only defined under CONFIG_PPC64:\n\n arch/powerpc/include/asm/entry-common.h:273: error: implicit\n declaration of function \u0027irq_soft_mask_set\u0027\n\n Using hard_irq_disable() requires no #ifdef and is consistent with\n how the rest of the entry code (e.g. entry-common.h:463) handles the\n same PPC32/PPC64 split.",
"id": "GHSA-c6r3-334m-j754",
"modified": "2026-10-14T15:32:19Z",
"published": "2026-10-14T15:32:19Z",
"references": [
{
"type": "ADVISORY",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2026-98395"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/63a7531ca31f9f097d9cc1cc3fe86ae683cdabdd"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/95cd316a896f1c1aa4ee4a817ba3d4691103c81b"
}
],
"schema_version": "1.4.0",
"severity": []
}
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