GHSA-9P4V-MQ4J-FJV8
Vulnerability from github – Published: 2026-08-28 09:31 – Updated: 2026-08-28 09:31In the Linux kernel, the following vulnerability has been resolved:
spi: spi-qpic-snand: write the feature value before executing SET_FEATURE
qcom_spi_send_cmdaddr() programs NAND_FLASH_CMD/NAND_EXEC_CMD and submits the descriptors, which makes the controller execute the command immediately. For SPINAND_SET_FEATURE the value to be written is only placed into NAND_FLASH_FEATURES afterwards, by qcom_spi_io_op(), in a second submission - so the chip is programmed with whatever that register happened to hold from a previous operation, and the intended value is only applied by the next SET_FEATURE.
Measured on a TP-Link Archer AX55 v1 (IPQ5018, ESMT F50L1G41LB): writing 0x40 to the configuration register (0xb0) leaves the chip at 0x00, and the subsequent write of 0x00 leaves it at 0x40 - every write lands one operation late.
This stayed unnoticed until v6.18 added SPI-NAND OTP support together with OTP entries for ESMT chips. spinand_otp_rw() enables OTP mode, reads, and disables it again, and mtd_otp_nvmem_add() does this during MTD registration. With the off-by-one, the "disable" write actually applies the previously requested value, so CFG_OTP_ENABLE ends up set: the chip stays in OTP mode, every subsequent array read returns the OTP area instead of the array (UBI reports an empty device) and all writes fail with -EIO because the OTP area is write protected. On this board that makes the whole flash unusable and the device unbootable.
Write the feature value into NAND_FLASH_FEATURES as part of the same transaction, before NAND_EXEC_CMD. While at it, copy only the bytes the operation actually carries - the previous code dereferenced a 4-byte pointer on a one-byte buffer (spinand->scratchbuf).
With this patch the flash contents read back bit-identical to a known-good dump of the same board taken under the vendor firmware (md5-verified across partitions), and writes work.
{
"affected": [],
"aliases": [
"CVE-2026-80712"
],
"database_specific": {
"cwe_ids": [],
"github_reviewed": false,
"github_reviewed_at": null,
"nvd_published_at": "2026-08-28T08:16:56Z",
"severity": null
},
"details": "In the Linux kernel, the following vulnerability has been resolved:\n\nspi: spi-qpic-snand: write the feature value before executing SET_FEATURE\n\nqcom_spi_send_cmdaddr() programs NAND_FLASH_CMD/NAND_EXEC_CMD and submits\nthe descriptors, which makes the controller execute the command\nimmediately. For SPINAND_SET_FEATURE the value to be written is only\nplaced into NAND_FLASH_FEATURES afterwards, by qcom_spi_io_op(), in a\nsecond submission - so the chip is programmed with whatever that register\nhappened to hold from a previous operation, and the intended value is only\napplied by the *next* SET_FEATURE.\n\nMeasured on a TP-Link Archer AX55 v1 (IPQ5018, ESMT F50L1G41LB): writing\n0x40 to the configuration register (0xb0) leaves the chip at 0x00, and the\nsubsequent write of 0x00 leaves it at 0x40 - every write lands one\noperation late.\n\nThis stayed unnoticed until v6.18 added SPI-NAND OTP support together\nwith OTP entries for ESMT chips. spinand_otp_rw() enables OTP mode,\nreads, and disables it again, and mtd_otp_nvmem_add() does this during\nMTD registration. With the off-by-one, the \"disable\" write actually\napplies the previously requested value, so CFG_OTP_ENABLE ends up set:\nthe chip stays in OTP mode, every subsequent array read returns the OTP\narea instead of the array (UBI reports an empty device) and all writes\nfail with -EIO because the OTP area is write protected. On this board\nthat makes the whole flash unusable and the device unbootable.\n\nWrite the feature value into NAND_FLASH_FEATURES as part of the same\ntransaction, before NAND_EXEC_CMD. While at it, copy only the bytes the\noperation actually carries - the previous code dereferenced a 4-byte\npointer on a one-byte buffer (spinand-\u003escratchbuf).\n\nWith this patch the flash contents read back bit-identical to a\nknown-good dump of the same board taken under the vendor firmware\n(md5-verified across partitions), and writes work.",
"id": "GHSA-9p4v-mq4j-fjv8",
"modified": "2026-08-28T09:31:50Z",
"published": "2026-08-28T09:31:50Z",
"references": [
{
"type": "ADVISORY",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2026-80712"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/3ba021079ef2ac6e21e3547328496ac42d22b56a"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/581e5166f0780103dc91c0d8ebc801f9af4824b0"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/8fd62901d6bf03f274a49dd0060793cc07dd51b0"
}
],
"schema_version": "1.4.0",
"severity": []
}
Sightings
| Author | Source | Type | Date | Other |
|---|
Nomenclature
- Seen: The vulnerability was mentioned, discussed, or observed by the user.
- Confirmed: The vulnerability has been validated from an analyst's perspective.
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- Not confirmed: The user expressed doubt about the validity of the vulnerability.
- Not patched: The vulnerability was not observed as successfully patched by the user who reported the sighting.
The approach is described in our paper Mapping CVEs to MITRE ATT&CK Techniques: A Curated Gold-Set Classifier and the Limits of LLM-Assisted Label Expansion.