GHSA-68Q2-CR9G-X9R8
Vulnerability from github – Published: 2026-09-17 18:32 – Updated: 2026-09-17 18:32In the Linux kernel, the following vulnerability has been resolved:
serial: qcom-geni: do not advance stale DMA completions
The qcom GENI serial DMA TX completion path advances the transmit fifo by the number of bytes recorded in port->tx_remaining.
If uart_flush_buffer() runs after the hardware has completed a DMA transfer but before the DMA completion interrupt has been handled, the serial core resets the transmit fifo while port->tx_remaining still describes the old DMA transfer.
A previous fix avoided advancing an empty fifo by checking that the fifo length is at least tx_remaining. That still does not distinguish the old DMA payload from new bytes written after the flush. If userspace writes new data before the stale DMA completion interrupt is handled, the fifo can again contain at least tx_remaining bytes and the stale completion can advance and discard those new bytes.
Mark an in-flight DMA transfer stale when the transmit fifo is flushed. The later completion still unprepares the original DMA mapping using the saved length, but it no longer advances the transmit fifo.
{
"affected": [],
"aliases": [
"CVE-2026-93123"
],
"database_specific": {
"cwe_ids": [],
"github_reviewed": false,
"github_reviewed_at": null,
"nvd_published_at": "2026-09-17T17:18:07Z",
"severity": null
},
"details": "In the Linux kernel, the following vulnerability has been resolved:\n\nserial: qcom-geni: do not advance stale DMA completions\n\nThe qcom GENI serial DMA TX completion path advances the transmit fifo by\nthe number of bytes recorded in port-\u003etx_remaining.\n\nIf uart_flush_buffer() runs after the hardware has completed a DMA\ntransfer but before the DMA completion interrupt has been handled, the\nserial core resets the transmit fifo while port-\u003etx_remaining still\ndescribes the old DMA transfer.\n\nA previous fix avoided advancing an empty fifo by checking that the fifo\nlength is at least tx_remaining. That still does not distinguish the old\nDMA payload from new bytes written after the flush. If userspace writes\nnew data before the stale DMA completion interrupt is handled, the fifo\ncan again contain at least tx_remaining bytes and the stale completion\ncan advance and discard those new bytes.\n\nMark an in-flight DMA transfer stale when the transmit fifo is flushed.\nThe later completion still unprepares the original DMA mapping using the\nsaved length, but it no longer advances the transmit fifo.",
"id": "GHSA-68q2-cr9g-x9r8",
"modified": "2026-09-17T18:32:11Z",
"published": "2026-09-17T18:32:11Z",
"references": [
{
"type": "ADVISORY",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2026-93123"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/231c84fe7ec40e4a06c398c0591d5b8e823d68e1"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/59faa59c25a0a098fbc86275408d7c8405015702"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/7ea38c49e7178960926657863299face6dc0e1b0"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/c02d030747c46da33faf406dd772ef91100efa27"
}
],
"schema_version": "1.4.0",
"severity": []
}
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