GHSA-45JC-GXG9-3GVC
Vulnerability from github – Published: 2026-09-16 12:30 – Updated: 2026-10-21 15:41In the Linux kernel, the following vulnerability has been resolved:
drm/amdgpu: force complete the MES ring fences on reset
The MES scheduler ring has no drm scheduler (no_scheduler = true), so it is skipped by the force-completion loop in amdgpu_device_pre_asic_reset(). It uses a polling fence whose hw value lives in wb (GTT) memory and survives a MODE1 reset, while fence_drv.sync_seq keeps advancing for every packet.
When the reset is triggered because MES itself stopped responding, the timed-out packets advance sync_seq past the last hw fence value MES wrote. After resume the first MES submission polls forever on a seq that is never written back, failing the resume and wedging the box on a second reset:
amdgpu: MES ring buffer is full. amdgpu: ERROR ring gfx_0.0.0 test failed (-110) amdgpu: resume of IP block failed -110 amdgpu: GPU reset end with ret = -110
Force complete the MES scheduler ring fences together with the scheduler rings so their hw fence is realigned to sync_seq.
v2: cover all XCCs (one scheduler ring each), not just mes.ring[0].
{
"affected": [],
"aliases": [
"CVE-2026-89812"
],
"database_specific": {
"cwe_ids": [],
"github_reviewed": false,
"github_reviewed_at": null,
"nvd_published_at": "2026-09-16T11:16:46Z",
"severity": null
},
"details": "In the Linux kernel, the following vulnerability has been resolved:\n\ndrm/amdgpu: force complete the MES ring fences on reset\n\nThe MES scheduler ring has no drm scheduler (no_scheduler = true), so it is\nskipped by the force-completion loop in amdgpu_device_pre_asic_reset(). It uses\na polling fence whose hw value lives in wb (GTT) memory and survives a MODE1\nreset, while fence_drv.sync_seq keeps advancing for every packet.\n\nWhen the reset is triggered because MES itself stopped responding, the\ntimed-out packets advance sync_seq past the last hw fence value MES wrote.\nAfter resume the first MES submission polls forever on a seq that is never\nwritten back, failing the resume and wedging the box on a second reset:\n\n amdgpu: MES ring buffer is full.\n amdgpu: *ERROR* ring gfx_0.0.0 test failed (-110)\n amdgpu: resume of IP block \u003cgfx_v11_0\u003e failed -110\n amdgpu: GPU reset end with ret = -110\n\nForce complete the MES scheduler ring fences together with the scheduler rings\nso their hw fence is realigned to sync_seq.\n\nv2: cover all XCCs (one scheduler ring each), not just mes.ring[0].",
"id": "GHSA-45jc-gxg9-3gvc",
"modified": "2026-10-21T15:41:13Z",
"published": "2026-09-16T12:30:37Z",
"references": [
{
"type": "ADVISORY",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2026-89812"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/48dc279c3010ac8f91b1845b2abb3a1e9943a0f5"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/7d722821e2f626c4e34c8510f0ce1d6f10c77a3b"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/c48d5a4d2863e56a6692ecb6cd6c32404f40cd0f"
},
{
"type": "WEB",
"url": "https://git.kernel.org/stable/c/ebe7542553d008e2285e0fbba0c63f0295a7e694"
}
],
"schema_version": "1.4.0",
"severity": []
}
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