FKIE_CVE-2025-39961
Vulnerability from fkie_nvd - Published: 2025-10-09 13:15 - Updated: 2026-10-19 21:10
Severity
8.8 (High) - CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H
4.7 (Medium) - CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:U/C:N/I:N/A:H
4.7 (Medium) - CVSS:3.1/
Summary
In the Linux kernel, the following vulnerability has been resolved:
iommu/amd/pgtbl: Fix possible race while increase page table level
The AMD IOMMU host page table implementation supports dynamic page table levels
(up to 6 levels), starting with a 3-level configuration that expands based on
IOVA address. The kernel maintains a root pointer and current page table level
to enable proper page table walks in alloc_pte()/fetch_pte() operations.
The IOMMU IOVA allocator initially starts with 32-bit address and onces its
exhuasted it switches to 64-bit address (max address is determined based
on IOMMU and device DMA capability). To support larger IOVA, AMD IOMMU
driver increases page table level.
But in unmap path (iommu_v1_unmap_pages()), fetch_pte() reads
pgtable->[root/mode] without lock. So its possible that in exteme corner case,
when increase_address_space() is updating pgtable->[root/mode], fetch_pte()
reads wrong page table level (pgtable->mode). It does compare the value with
level encoded in page table and returns NULL. This will result is
iommu_unmap ops to fail and upper layer may retry/log WARN_ON.
CPU 0 CPU 1
------ ------
map pages unmap pages
alloc_pte() -> increase_address_space() iommu_v1_unmap_pages() -> fetch_pte()
pgtable->root = pte (new root value)
READ pgtable->[mode/root]
Reads new root, old mode
Updates mode (pgtable->mode += 1)
Since Page table level updates are infrequent and already synchronized with a
spinlock, implement seqcount to enable lock-free read operations on the read path.
References
Impacted products
| Vendor | Product | Version | |
|---|---|---|---|
| linux | linux_kernel | * | |
| linux | linux_kernel | * | |
| linux | linux_kernel | * | |
| linux | linux_kernel | * | |
| linux | linux_kernel | * | |
| linux | linux_kernel | * | |
| linux | linux_kernel | * | |
| linux | linux_kernel | 5.3 | |
| linux | linux_kernel | 5.3 | |
| linux | linux_kernel | 6.17 | |
| linux | linux_kernel | 6.17 | |
| linux | linux_kernel | 6.17 | |
| linux | linux_kernel | 6.17 | |
| linux | linux_kernel | 6.17 | |
| linux | linux_kernel | 6.17 |
{
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{
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"product": "Linux",
"programFiles": [
"drivers/iommu/amd/amd_iommu_types.h",
"drivers/iommu/amd/io_pgtable.c"
],
"repo": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
"vendor": "Linux",
"versions": [
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{
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"version": "0d50f7b1e8c80a8c20db5049e269468c059b0378",
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{
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"version": "785ca708a908b9c596ede852470ba28b8dc3e40b",
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},
{
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"version": "4.9.194",
"versionType": "semver"
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{
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"version": "4.14.146",
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{
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"version": "4.19.75",
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{
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]
},
{
"defaultStatus": "affected",
"product": "Linux",
"programFiles": [
"drivers/iommu/amd/amd_iommu_types.h",
"drivers/iommu/amd/io_pgtable.c"
],
"repo": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
"vendor": "Linux",
"versions": [
{
"status": "affected",
"version": "5.3"
},
{
"lessThan": "5.3",
"status": "unaffected",
"version": "0",
"versionType": "semver"
},
{
"lessThanOrEqual": "6.6.*",
"status": "unaffected",
"version": "6.6.108",
"versionType": "semver"
},
{
"lessThanOrEqual": "6.12.*",
"status": "unaffected",
"version": "6.12.49",
"versionType": "semver"
},
{
"lessThanOrEqual": "6.16.*",
"status": "unaffected",
"version": "6.16.9",
"versionType": "semver"
},
{
"lessThanOrEqual": "*",
"status": "unaffected",
"version": "6.17",
"versionType": "original_commit_for_fix"
}
]
}
],
"source": "416baaa9-dc9f-4396-8d5f-8c081fb06d67"
}
],
"configurations": [
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"cveTags": [],
"descriptions": [
{
"lang": "en",
"value": "In the Linux kernel, the following vulnerability has been resolved:\n\niommu/amd/pgtbl: Fix possible race while increase page table level\n\nThe AMD IOMMU host page table implementation supports dynamic page table levels\n(up to 6 levels), starting with a 3-level configuration that expands based on\nIOVA address. The kernel maintains a root pointer and current page table level\nto enable proper page table walks in alloc_pte()/fetch_pte() operations.\n\nThe IOMMU IOVA allocator initially starts with 32-bit address and onces its\nexhuasted it switches to 64-bit address (max address is determined based\non IOMMU and device DMA capability). To support larger IOVA, AMD IOMMU\ndriver increases page table level.\n\nBut in unmap path (iommu_v1_unmap_pages()), fetch_pte() reads\npgtable-\u003e[root/mode] without lock. So its possible that in exteme corner case,\nwhen increase_address_space() is updating pgtable-\u003e[root/mode], fetch_pte()\nreads wrong page table level (pgtable-\u003emode). It does compare the value with\nlevel encoded in page table and returns NULL. This will result is\niommu_unmap ops to fail and upper layer may retry/log WARN_ON.\n\nCPU 0 CPU 1\n------ ------\nmap pages unmap pages\nalloc_pte() -\u003e increase_address_space() iommu_v1_unmap_pages() -\u003e fetch_pte()\n pgtable-\u003eroot = pte (new root value)\n READ pgtable-\u003e[mode/root]\n\t\t\t\t\t Reads new root, old mode\n Updates mode (pgtable-\u003emode += 1)\n\nSince Page table level updates are infrequent and already synchronized with a\nspinlock, implement seqcount to enable lock-free read operations on the read path."
},
{
"lang": "es",
"value": "En el kernel de Linux, la siguiente vulnerabilidad ha sido resuelta:\n\niommu/amd/pgtbl: Corrige una posible condici\u00f3n de carrera al aumentar el nivel de la tabla de p\u00e1ginas\n\nLa implementaci\u00f3n de la tabla de p\u00e1ginas de host de AMD IOMMU soporta niveles de tabla de p\u00e1ginas din\u00e1micos (hasta 6 niveles), comenzando con una configuraci\u00f3n de 3 niveles que se expande bas\u00e1ndose en la direcci\u00f3n IOVA. El kernel mantiene un puntero ra\u00edz y el nivel actual de la tabla de p\u00e1ginas para permitir recorridos adecuados de la tabla de p\u00e1ginas en las operaciones alloc_pte()/fetch_pte().\n\nEl asignador IOVA de IOMMU inicialmente comienza con una direcci\u00f3n de 32 bits y una vez que se agota, cambia a una direcci\u00f3n de 64 bits (la direcci\u00f3n m\u00e1xima se determina bas\u00e1ndose en la capacidad DMA del IOMMU y del dispositivo). Para soportar IOVA m\u00e1s grandes, el controlador AMD IOMMU aumenta el nivel de la tabla de p\u00e1ginas.\n\nPero en la ruta de desmapeo (iommu_v1_unmap_pages()), fetch_pte() lee pgtable-\u003e[root/mode] sin bloqueo. As\u00ed que es posible que en un caso extremo, cuando increase_address_space() est\u00e1 actualizando pgtable-\u003e[root/mode], fetch_pte() lea un nivel de tabla de p\u00e1ginas incorrecto (pgtable-\u003emode). Compara el valor con el nivel codificado en la tabla de p\u00e1ginas y devuelve NULL. Esto resultar\u00e1 en que las operaciones iommu_unmap fallen y la capa superior puede reintentar/registrar WARN_ON.\n\nCPU 0 CPU 1\n------ ------\nmapear p\u00e1ginas desmapear p\u00e1ginas\nalloc_pte() -\u003e increase_address_space() iommu_v1_unmap_pages() -\u003e fetch_pte()\n pgtable-\u003eroot = pte (nuevo valor ra\u00edz)\n LEER pgtable-\u003e[mode/root]\n\t\t\t\t\t Lee nueva ra\u00edz, modo antiguo\n Actualiza el modo (pgtable-\u003emode += 1)\n\nDado que las actualizaciones del nivel de la tabla de p\u00e1ginas son poco frecuentes y ya est\u00e1n sincronizadas con un spinlock, se implementa seqcount para habilitar operaciones de lectura sin bloqueo en la ruta de lectura."
}
],
"id": "CVE-2025-39961",
"lastModified": "2026-10-19T21:10:00.160",
"metrics": {
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"attackComplexity": "LOW",
"attackVector": "LOCAL",
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"baseScore": 8.8,
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"confidentialityImpact": "HIGH",
"integrityImpact": "HIGH",
"privilegesRequired": "LOW",
"scope": "CHANGED",
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"vectorString": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H",
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"source": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
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"impactScore": 3.6,
"source": "nvd@nist.gov",
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"ssvcV203": [
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"source": "134c704f-9b21-4f2e-91b3-4a467353bcc0",
"ssvcData": {
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"options": [
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{
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{
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],
"role": "CISA Coordinator",
"timestamp": "2026-10-15T21:55:10.295299Z",
"version": "2.0.3"
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},
"published": "2025-10-09T13:15:32.250",
"references": [
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"source": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
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"value": "CWE-362"
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}
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Sightings
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The MITRE ATT&CK techniques below are AI-generated suggestions, inferred from the description of the
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The approach is described in our paper Mapping CVEs to MITRE ATT&CK Techniques: A Curated Gold-Set Classifier and the Limits of LLM-Assisted Label Expansion.
Browse all ATT&CK techniques and the vulnerabilities related to each.
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