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CVE-2019-11135 (GCVE-0-2019-11135)
Vulnerability from cvelistv5 – Published: 2019-11-14 18:19 – Updated: 2026-05-28 18:21- Information Disclosure
- CWE-noinfo Not enough information
| Vendor | Product | Version | |
|---|---|---|---|
| n/a | 2019.2 IPU – TSX Asynchronous Abort |
Affected:
See provided reference
|
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RHSA-2019:3840
Vulnerability from csaf_redhat - Published: 2019-11-12 21:22 - Updated: 2026-05-28 20:36A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 7Server-7.3.AUS:kernel-0:3.10.0-514.70.2.el7.src | — |
Vendor Fix
fix
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| Unresolved product id: 7Server-7.3.AUS:kernel-0:3.10.0-514.70.2.el7.x86_64 | — |
Vendor Fix
fix
Workaround
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| Unresolved product id: 7Server-7.3.AUS:kernel-abi-whitelists-0:3.10.0-514.70.2.el7.noarch | — |
Vendor Fix
fix
Workaround
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| Unresolved product id: 7Server-7.3.AUS:kernel-debug-0:3.10.0-514.70.2.el7.x86_64 | — |
Vendor Fix
fix
Workaround
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| Unresolved product id: 7Server-7.3.AUS:kernel-debug-debuginfo-0:3.10.0-514.70.2.el7.x86_64 | — |
Vendor Fix
fix
Workaround
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| Unresolved product id: 7Server-7.3.AUS:kernel-debug-devel-0:3.10.0-514.70.2.el7.x86_64 | — |
Vendor Fix
fix
Workaround
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A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
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{
"acknowledgments": [
{
"names": [
"Intel"
]
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{
"names": [
"Deepak Gupta"
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"summary": "Acknowledged by upstream."
}
],
"cve": "CVE-2018-12207",
"cwe": {
"id": "CWE-226",
"name": "Sensitive Information in Resource Not Removed Before Reuse"
},
"discovery_date": "2018-11-06T00:00:00+00:00",
"ids": [
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"system_name": "Red Hat Bugzilla ID",
"text": "1646768"
}
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{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2018-12207"
},
{
"category": "external",
"summary": "RHBZ#1646768",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1646768"
},
{
"category": "external",
"summary": "RHSB-ifu-page-mce",
"url": "https://access.redhat.com/security/vulnerabilities/ifu-page-mce"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2018-12207",
"url": "https://www.cve.org/CVERecord?id=CVE-2018-12207"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:22:53+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3840"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat vulnerability article: https://access.redhat.com/security/vulnerabilities/ifu-page-mce .",
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"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "hw: Machine Check Error on Page Size Change (IFU)"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-0154",
"cwe": {
"id": "CWE-284",
"name": "Improper Access Control"
},
"discovery_date": "2019-06-27T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1724393"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "Intel plans to release BIOS firmware to correct this issue. Red Hat\u0027s kernel update should mitigate this vulnerability. Some older hardware will not have BIOS firmware update and will rely on operating system level protection to prevent access while the device is in low-power states. For more information see https://access.redhat.com/solutions/i915-graphics",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-0154"
},
{
"category": "external",
"summary": "RHBZ#1724393",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1724393"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-0154",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-0154"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/i915-graphics",
"url": "https://access.redhat.com/solutions/i915-graphics"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:22:53+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3840"
},
{
"category": "workaround",
"details": "Preventing loading of the i915 kernel module will prevent attackers from using this exploit against the system however the power management functionality of the card will be disabled and the system may draw additional power. See this KCS article (https://access.redhat.com/solutions/41278) for instructions on how to disable a kernel module. Graphical displays may also be at low resolution or not work correctly. This mitigation may not be suitable if running graphical tools locally is required.",
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{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-11135",
"cwe": {
"id": "CWE-385",
"name": "Covert Timing Channel"
},
"discovery_date": "2019-09-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-11135"
},
{
"category": "external",
"summary": "RHBZ#1753062",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1753062"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-11135",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
"url": "https://access.redhat.com/solutions/tsx-asynchronousabort"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:22:53+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3840"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat Knowledgebase article: https://access.redhat.com/solutions/tsx-asynchronousabort",
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"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
},
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}
],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
}
]
}
RHSA-2019:3841
Vulnerability from csaf_redhat - Published: 2019-11-12 21:02 - Updated: 2026-05-28 20:36A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
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A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.
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A flaw was found in the Intel graphics hardware (GPU), where a local attacker with the ability to issue commands to the GPU could inadvertently lead to memory corruption and possible privilege escalation. The attacker could use the GPU blitter to perform privilege MMIO operations, not limited to the address space required to function correctly.
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
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{
"acknowledgments": [
{
"names": [
"Intel"
]
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{
"names": [
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"summary": "Acknowledged by upstream."
}
],
"cve": "CVE-2018-12207",
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"id": "CWE-226",
"name": "Sensitive Information in Resource Not Removed Before Reuse"
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"discovery_date": "2018-11-06T00:00:00+00:00",
"ids": [
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"system_name": "Red Hat Bugzilla ID",
"text": "1646768"
}
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{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2018-12207"
},
{
"category": "external",
"summary": "RHBZ#1646768",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1646768"
},
{
"category": "external",
"summary": "RHSB-ifu-page-mce",
"url": "https://access.redhat.com/security/vulnerabilities/ifu-page-mce"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2018-12207",
"url": "https://www.cve.org/CVERecord?id=CVE-2018-12207"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:02:11+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3841"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat vulnerability article: https://access.redhat.com/security/vulnerabilities/ifu-page-mce .",
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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],
"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "hw: Machine Check Error on Page Size Change (IFU)"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-0154",
"cwe": {
"id": "CWE-284",
"name": "Improper Access Control"
},
"discovery_date": "2019-06-27T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1724393"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "Intel plans to release BIOS firmware to correct this issue. Red Hat\u0027s kernel update should mitigate this vulnerability. Some older hardware will not have BIOS firmware update and will rely on operating system level protection to prevent access while the device is in low-power states. For more information see https://access.redhat.com/solutions/i915-graphics",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-0154"
},
{
"category": "external",
"summary": "RHBZ#1724393",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1724393"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-0154",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-0154"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/i915-graphics",
"url": "https://access.redhat.com/solutions/i915-graphics"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:02:11+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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],
"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3841"
},
{
"category": "workaround",
"details": "Preventing loading of the i915 kernel module will prevent attackers from using this exploit against the system however the power management functionality of the card will be disabled and the system may draw additional power. See this KCS article (https://access.redhat.com/solutions/41278) for instructions on how to disable a kernel module. Graphical displays may also be at low resolution or not work correctly. This mitigation may not be suitable if running graphical tools locally is required.",
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"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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}
],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-0155",
"cwe": {
"id": "CWE-284",
"name": "Improper Access Control"
},
"discovery_date": "2019-06-27T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1724398"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the Intel graphics hardware (GPU), where a local attacker with the ability to issue commands to the GPU could inadvertently lead to memory corruption and possible privilege escalation. The attacker could use the GPU blitter to perform privilege MMIO operations, not limited to the address space required to function correctly.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Intel GPU blitter manipulation can allow for arbitrary kernel memory write",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "Red Hat Product Security is aware of this issue. Updates will be released as they become available. For additional information, please refer to the Red Hat Knowledgebase article: https://access.redhat.com/solutions/i915-graphics",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-0155"
},
{
"category": "external",
"summary": "RHBZ#1724398",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1724398"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-0155",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-0155"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-0155",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-0155"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/i915-graphics",
"url": "https://access.redhat.com/solutions/i915-graphics"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00242.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00242.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:02:11+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3841"
},
{
"category": "workaround",
"details": "Preventing loading of the i915 kernel module will prevent attackers from using this exploit against the system however the power management functionality of the card will be disabled and the system may draw additional power. See this KCS article( https://access.redhat.com/solutions/41278 ) for instructions on how to disable a kernel module. Graphical displays may also be at low resolution or not work correctly. This mitigation may not be suitable if running graphical tools locally is required.",
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],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 8.8,
"baseSeverity": "HIGH",
"confidentialityImpact": "HIGH",
"integrityImpact": "HIGH",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H",
"version": "3.0"
},
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"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "hw: Intel GPU blitter manipulation can allow for arbitrary kernel memory write"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-11135",
"cwe": {
"id": "CWE-385",
"name": "Covert Timing Channel"
},
"discovery_date": "2019-09-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-11135"
},
{
"category": "external",
"summary": "RHBZ#1753062",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1753062"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-11135",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
"url": "https://access.redhat.com/solutions/tsx-asynchronousabort"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:02:11+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3841"
},
{
"category": "workaround",
"details": "For mitigation related information, please refer to the Red Hat Knowledgebase article: https://access.redhat.com/solutions/tsx-asynchronousabort",
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}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
},
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]
}
],
"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
}
]
}
RHSA-2019:3842
Vulnerability from csaf_redhat - Published: 2019-11-12 21:11 - Updated: 2026-05-28 20:36A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
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{
"document": {
"aggregate_severity": {
"namespace": "https://access.redhat.com/security/updates/classification/",
"text": "Important"
},
"category": "csaf_security_advisory",
"csaf_version": "2.0",
"distribution": {
"text": "Copyright \u00a9 Red Hat, Inc. All rights reserved.",
"tlp": {
"label": "WHITE",
"url": "https://www.first.org/tlp/"
}
},
"lang": "en",
"notes": [
{
"category": "summary",
"text": "An update for kernel is now available for Red Hat Enterprise Linux 6.6 Advanced Update Support.\n\nRed Hat Product Security has rated this update as having a security impact of Important. A Common Vulnerability Scoring System (CVSS) base score, which gives a detailed severity rating, is available for each vulnerability from the CVE link(s) in the References section.",
"title": "Topic"
},
{
"category": "general",
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"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
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"text": "hw: Machine Check Error on Page Size Change (IFU)",
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{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
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{
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{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-11135",
"cwe": {
"id": "CWE-385",
"name": "Covert Timing Channel"
},
"discovery_date": "2019-09-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-11135"
},
{
"category": "external",
"summary": "RHBZ#1753062",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1753062"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-11135",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
"url": "https://access.redhat.com/solutions/tsx-asynchronousabort"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:11:25+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"restart_required": {
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},
{
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"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
},
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"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
}
]
}
RHSA-2019:3843
Vulnerability from csaf_redhat - Published: 2019-11-12 21:12 - Updated: 2026-05-28 20:36A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
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| Unresolved product id: 6Server-6.5.AUS:kernel-0:2.6.32-431.96.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-6.5.AUS:kernel-abi-whitelists-0:2.6.32-431.96.3.el6.noarch | — |
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|
|
| Unresolved product id: 6Server-6.5.AUS:kernel-debug-0:2.6.32-431.96.3.el6.x86_64 | — |
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fix
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|
|
| Unresolved product id: 6Server-6.5.AUS:kernel-debug-debuginfo-0:2.6.32-431.96.3.el6.x86_64 | — |
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fix
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|
|
| Unresolved product id: 6Server-6.5.AUS:kernel-debug-devel-0:2.6.32-431.96.3.el6.x86_64 | — |
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fix
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|
|
| Unresolved product id: 6Server-6.5.AUS:kernel-debuginfo-0:2.6.32-431.96.3.el6.x86_64 | — |
Vendor Fix
fix
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|
|
| Unresolved product id: 6Server-6.5.AUS:kernel-debuginfo-common-x86_64-0:2.6.32-431.96.3.el6.x86_64 | — |
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fix
Workaround
|
|
| Unresolved product id: 6Server-6.5.AUS:kernel-devel-0:2.6.32-431.96.3.el6.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-6.5.AUS:kernel-doc-0:2.6.32-431.96.3.el6.noarch | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-6.5.AUS:kernel-firmware-0:2.6.32-431.96.3.el6.noarch | — |
Vendor Fix
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Workaround
|
|
| Unresolved product id: 6Server-6.5.AUS:perf-0:2.6.32-431.96.3.el6.x86_64 | — |
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|
|
| Unresolved product id: 6Server-6.5.AUS:perf-debuginfo-0:2.6.32-431.96.3.el6.x86_64 | — |
Vendor Fix
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| Unresolved product id: 6Server-6.5.AUS:python-perf-0:2.6.32-431.96.3.el6.x86_64 | — |
Vendor Fix
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| Unresolved product id: 6Server-6.5.AUS:python-perf-debuginfo-0:2.6.32-431.96.3.el6.x86_64 | — |
Vendor Fix
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Workaround
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|
| Unresolved product id: 6Server-optional-6.5.AUS:kernel-0:2.6.32-431.96.3.el6.src | — |
Vendor Fix
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Workaround
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| Unresolved product id: 6Server-optional-6.5.AUS:kernel-0:2.6.32-431.96.3.el6.x86_64 | — |
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| Unresolved product id: 6Server-optional-6.5.AUS:kernel-abi-whitelists-0:2.6.32-431.96.3.el6.noarch | — |
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|
| Unresolved product id: 6Server-optional-6.5.AUS:kernel-debug-0:2.6.32-431.96.3.el6.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 6Server-optional-6.5.AUS:kernel-debug-debuginfo-0:2.6.32-431.96.3.el6.x86_64 | — |
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fix
Workaround
|
|
| Unresolved product id: 6Server-optional-6.5.AUS:kernel-debug-devel-0:2.6.32-431.96.3.el6.x86_64 | — |
Vendor Fix
fix
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
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"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
{
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"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
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"title": "hw: Machine Check Error on Page Size Change (IFU)"
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"names": [
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],
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"ids": [
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"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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{
"category": "external",
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{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-11135",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
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{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
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"category": "vendor_fix",
"date": "2019-11-12T21:12:23+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
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"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
}
]
}
RHSA-2019:3844
Vulnerability from csaf_redhat - Published: 2019-11-12 21:08 - Updated: 2026-05-28 20:36A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-1:3.10.0-693.60.2.rt56.655.el6rt.src | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debuginfo-common-x86_64-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-doc-1:3.10.0-693.60.2.rt56.655.el6rt.noarch | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-firmware-1:3.10.0-693.60.2.rt56.655.el6rt.noarch | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.
| Product | Identifier | Version | Remediation |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-1:3.10.0-693.60.2.rt56.655.el6rt.src | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debuginfo-common-x86_64-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-doc-1:3.10.0-693.60.2.rt56.655.el6rt.noarch | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-firmware-1:3.10.0-693.60.2.rt56.655.el6rt.noarch | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-1:3.10.0-693.60.2.rt56.655.el6rt.src | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debug-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-debuginfo-common-x86_64-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-doc-1:3.10.0-693.60.2.rt56.655.el6rt.noarch | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-firmware-1:3.10.0-693.60.2.rt56.655.el6rt.noarch | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-trace-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-debuginfo-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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| Unresolved product id: 6Server-MRG-Realtime-2:kernel-rt-vanilla-devel-1:3.10.0-693.60.2.rt56.655.el6rt.x86_64 | — |
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{
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"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
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"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
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"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html"
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"version": "3.0"
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"title": "hw: Machine Check Error on Page Size Change (IFU)"
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"name": "Improper Access Control"
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"ids": [
{
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"text": "1724393"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "Intel plans to release BIOS firmware to correct this issue. Red Hat\u0027s kernel update should mitigate this vulnerability. Some older hardware will not have BIOS firmware update and will rely on operating system level protection to prevent access while the device is in low-power states. For more information see https://access.redhat.com/solutions/i915-graphics",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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{
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"title": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state"
},
{
"acknowledgments": [
{
"names": [
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]
}
],
"cve": "CVE-2019-11135",
"cwe": {
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"name": "Covert Timing Channel"
},
"discovery_date": "2019-09-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1753062"
}
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"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-11135"
},
{
"category": "external",
"summary": "RHBZ#1753062",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1753062"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-11135",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
"url": "https://access.redhat.com/solutions/tsx-asynchronousabort"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2019-11-12T21:08:54+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"restart_required": {
"category": "none"
},
"url": "https://access.redhat.com/errata/RHSA-2019:3844"
},
{
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"scores": [
{
"cvss_v3": {
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"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
},
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"threats": [
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"details": "Moderate"
}
],
"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
}
]
}
RHSA-2019:3860
Vulnerability from csaf_redhat - Published: 2019-11-12 20:11 - Updated: 2026-05-28 20:36A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-virtualization-host-0:4.2-20191107.0.el7_6.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-virtualization-host-image-update-0:4.2-20191107.0.el7_6.noarch | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-Hypervisor-7:redhat-virtualization-host-0:4.3.6-20191108.0.el7_7.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-Hypervisor-7:redhat-virtualization-host-image-update-0:4.3.6-20191108.0.el7_7.noarch | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-virtualization-host-0:4.3.6-20191108.0.el7_7.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-virtualization-host-image-update-0:4.3.6-20191108.0.el7_7.noarch | — |
Vendor Fix
fix
Workaround
|
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.src | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.x86_64 | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-release-virtualization-host-content-0:4.2-16.1.el7.x86_64 | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-virtualization-host-image-update-placeholder-0:4.2-16.1.el7.noarch | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.src | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.x86_64 | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-release-virtualization-host-content-0:4.2-16.1.el7.x86_64 | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-virtualization-host-image-update-placeholder-0:4.2-16.1.el7.noarch | — |
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-release-virtualization-host-0:4.3.6-5.el7ev.src | — |
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-release-virtualization-host-0:4.3.6-5.el7ev.x86_64 | — |
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-virtualization-host-image-update-placeholder-0:4.3.6-5.el7ev.noarch | — |
Workaround
|
A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-virtualization-host-0:4.2-20191107.0.el7_6.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-virtualization-host-image-update-0:4.2-20191107.0.el7_6.noarch | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-Hypervisor-7:redhat-virtualization-host-0:4.3.6-20191108.0.el7_7.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-Hypervisor-7:redhat-virtualization-host-image-update-0:4.3.6-20191108.0.el7_7.noarch | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-virtualization-host-0:4.3.6-20191108.0.el7_7.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-virtualization-host-image-update-0:4.3.6-20191108.0.el7_7.noarch | — |
Vendor Fix
fix
Workaround
|
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.src | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.x86_64 | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-release-virtualization-host-content-0:4.2-16.1.el7.x86_64 | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-Hypervisor-eus:redhat-virtualization-host-image-update-placeholder-0:4.2-16.1.el7.noarch | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.src | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-release-virtualization-host-0:4.2-16.1.el7.x86_64 | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-release-virtualization-host-content-0:4.2-16.1.el7.x86_64 | — |
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS-RHV-4.2-HypervisorBuild-eus:redhat-virtualization-host-image-update-placeholder-0:4.2-16.1.el7.noarch | — |
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-release-virtualization-host-0:4.3.6-5.el7ev.src | — |
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-release-virtualization-host-0:4.3.6-5.el7ev.x86_64 | — |
Workaround
|
|
| Unresolved product id: 7Server-RHEV-4-HypervisorBuild-7:redhat-virtualization-host-image-update-placeholder-0:4.3.6-5.el7ev.noarch | — |
Workaround
|
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"text": "An update for redhat-release-virtualization-host and redhat-virtualization-host is now available for Red Hat Virtualization 4 for Red Hat Enterprise Linux 7 and Red Hat Virtualization 4.2 for Red Hat Enterprise Linux 7.6 EUS.\n\nRed Hat Product Security has rated this update as having a security impact of Important. A Common Vulnerability Scoring System (CVSS) base score, which gives a detailed severity rating, is available for each vulnerability from the CVE link(s) in the References section.",
"title": "Topic"
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"text": "The redhat-virtualization-host packages provide the Red Hat Virtualization Host. These packages include redhat-release-virtualization-host, ovirt-node, and rhev-hypervisor. Red Hat Virtualization Hosts (RHVH) are installed using a special build of Red Hat Enterprise Linux with only the packages required to host virtual machines. RHVH features a Cockpit user interface for monitoring the host\u0027s resources and performing administrative tasks. \n\nThe ovirt-node-ng packages provide the Red Hat Virtualization Host. These packages include redhat-release-virtualization-host, ovirt-node, and rhev-hypervisor. Red Hat Virtualization Hosts (RHVH) are installed using a special build of Red Hat Enterprise Linux with only the packages required to host virtual machines. RHVH features a Cockpit user interface for monitoring the host\u0027s resources and performing administrative tasks.\n\nSecurity Fix(es):\n\n* hw: Machine Check Error on Page Size Change (IFU) (CVE-2018-12207)\n\n* hw: TSX Transaction Asynchronous Abort (TAA) (CVE-2019-11135)\n\nFor more details about the security issue(s), including the impact, a CVSS score, and other related information, refer to the CVE page(s) listed in the References section.",
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"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2018-12207"
},
{
"category": "external",
"summary": "RHBZ#1646768",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1646768"
},
{
"category": "external",
"summary": "RHSB-ifu-page-mce",
"url": "https://access.redhat.com/security/vulnerabilities/ifu-page-mce"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2018-12207",
"url": "https://www.cve.org/CVERecord?id=CVE-2018-12207"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
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{
"category": "vendor_fix",
"date": "2019-11-12T20:11:55+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/2974891",
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"restart_required": {
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"url": "https://access.redhat.com/errata/RHSA-2019:3860"
},
{
"category": "workaround",
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"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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{
"category": "impact",
"details": "Important"
}
],
"title": "hw: Machine Check Error on Page Size Change (IFU)"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-11135",
"cwe": {
"id": "CWE-385",
"name": "Covert Timing Channel"
},
"discovery_date": "2019-09-18T00:00:00+00:00",
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"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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"url": "https://access.redhat.com/security/cve/CVE-2019-11135"
},
{
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"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1753062"
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{
"category": "external",
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"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
"url": "https://access.redhat.com/solutions/tsx-asynchronousabort"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
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"date": "2019-11-12T20:11:55+00:00",
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RHSA-2019:3936
Vulnerability from csaf_redhat - Published: 2019-11-22 08:52 - Updated: 2026-05-28 20:36A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-0:1-3.el8_1.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-0:1-3.el8_1.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-debuginfo-0:1-3.el8_1.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-debugsource-0:1-3.el8_1.x86_64 | — |
Vendor Fix
fix
Workaround
|
A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-0:1-3.el8_1.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-0:1-3.el8_1.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-debuginfo-0:1-3.el8_1.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: BaseOS-8.1.0.Z.MAIN.EUS:kpatch-patch-4_18_0-147-debugsource-0:1-3.el8_1.x86_64 | — |
Vendor Fix
fix
Workaround
|
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RHSA-2020:0026
Vulnerability from csaf_redhat - Published: 2020-01-06 14:16 - Updated: 2026-05-28 20:36A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_35_1-0:1-5.el7.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_35_1-0:1-5.el7.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_35_1-debuginfo-0:1-5.el7.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_35_2-0:1-4.el7.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_35_2-0:1-4.el7.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_35_2-debuginfo-0:1-4.el7.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_38_1-0:1-3.el7.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_38_1-0:1-3.el7.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_38_1-debuginfo-0:1-3.el7.x86_64 | — |
Vendor Fix
fix
Workaround
|
A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_35_1-0:1-5.el7.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_35_1-0:1-5.el7.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_35_1-debuginfo-0:1-5.el7.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_35_2-0:1-4.el7.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_35_2-0:1-4.el7.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_35_2-debuginfo-0:1-4.el7.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_38_1-0:1-3.el7.src | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_38_1-0:1-3.el7.x86_64 | — |
Vendor Fix
fix
Workaround
|
|
| Unresolved product id: 7Server-7.6.EUS:kpatch-patch-3_10_0-957_38_1-debuginfo-0:1-3.el7.x86_64 | — |
Vendor Fix
fix
Workaround
|
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"title": "Vulnerability description"
},
{
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"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
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"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
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RHSA-2020:0028
Vulnerability from csaf_redhat - Published: 2020-01-06 14:46 - Updated: 2026-05-28 20:36A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062-0:1-9.el7.src | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062-debuginfo-0:1-9.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_1_1-0:1-8.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_1_1-debuginfo-0:1-8.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_1_2-0:1-7.el7.src | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_1_2-0:1-7.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_1_2-debuginfo-0:1-7.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_4_1-0:1-4.el7.src | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_4_1-0:1-4.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_4_1-debuginfo-0:1-4.el7.x86_64 | — |
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
| Product | Identifier | Version | Remediation |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062-0:1-9.el7.src | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062-0:1-9.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062-debuginfo-0:1-9.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_1_1-0:1-8.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_1_1-debuginfo-0:1-8.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_1_2-0:1-7.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_1_2-debuginfo-0:1-7.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_4_1-0:1-4.el7.src | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_4_1-0:1-4.el7.x86_64 | — |
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| Unresolved product id: 7Server-7.7.Z:kpatch-patch-3_10_0-1062_4_1-debuginfo-0:1-4.el7.x86_64 | — |
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RHSA-2020:0204
Vulnerability from csaf_redhat - Published: 2020-01-22 21:26 - Updated: 2026-05-28 20:36A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU's local cache and system software's Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor. System software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor's Memory Management Unit (MMU) uses Paging structure entries to translate program's virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses. System software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor's TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.ppc64le | — |
Vendor Fix
fix
Workaround
|
|
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.src | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-abi-whitelists-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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A flaw was found in the Linux kernel's NFS41+ subsystem. NFS41+ shares mounted in different network namespaces at the same time can make bc_svc_process() use wrong back-channel IDs and cause a use-after-free vulnerability. Thus a malicious container user can cause a host kernel memory corruption and a system panic. Due to the nature of the flaw, privilege escalation cannot be fully ruled out.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.src | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-abi-whitelists-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-extra-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-extra-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.src | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-abi-whitelists-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-extra-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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A flaw was found in the Intel graphics hardware (GPU), where a local attacker with the ability to issue commands to the GPU could inadvertently lead to memory corruption and possible privilege escalation. The attacker could use the GPU blitter to perform privilege MMIO operations, not limited to the address space required to function correctly.
| Product | Identifier | Version | Remediation |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.src | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-abi-whitelists-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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An infinite loop issue was found in the vhost_net kernel module while handling incoming packets in handle_rx(). The infinite loop could occur if one end sends packets faster than the other end can process them. A guest user, maybe a remote one, could use this flaw to stall the vhost_net kernel thread, resulting in a DoS scenario.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.src | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-abi-whitelists-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-extra-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-extra-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-common-ppc64le-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-common-x86_64-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-devel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-devel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-doc-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-extra-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-extra-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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A new software page cache side channel attack scenario was discovered in operating systems that implement the very common 'page cache' caching mechanism. A malicious user/process could use 'in memory' page-cache knowledge to infer access timings to shared memory and gain knowledge which can be used to reduce effectiveness of cryptographic strength by monitoring algorithmic behavior, infer access patterns of memory to determine code paths taken, and exfiltrate data to a blinded attacker through page-granularity access times as a side-channel.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.src | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-abi-whitelists-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-extra-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-extra-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-common-ppc64le-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-common-x86_64-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-devel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-devel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-doc-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-extra-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-extra-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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A flaw was discovered in the Bluetooth protocol. An attacker within physical proximity to the Bluetooth connection could downgrade the encryption protocol to be trivially brute forced.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.src | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-abi-whitelists-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-extra-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-extra-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-common-ppc64le-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-common-x86_64-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-devel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-devel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-doc-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-extra-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-extra-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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A flaw was found in the mwifiex implementation in the Linux kernel. A system connecting to wireless access point could be manipulated by an attacker with advanced permissions on the access point into localized memory corruption or possibly privilege escalation.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.src | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-abi-whitelists-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution. While TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.
| Product | Identifier | Version | Remediation |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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A vulnerability was found in the Linux kernel's Marvell WiFi chip driver. Where, while parsing vendor-specific informational attributes, an attacker on the same WiFi physical network segment could cause a system crash, resulting in a denial of service, or potentially execute arbitrary code. This flaw affects the network interface at the most basic level meaning the attacker only needs to affiliate with the same network device as the vulnerable system to create an attack path.
| Product | Identifier | Version | Remediation |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.src | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-abi-whitelists-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-common-x86_64-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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An out-of-bounds access issue was found in the way Linux kernel's KVM hypervisor implements the Coalesced MMIO write operation. It operates on an MMIO ring buffer 'struct kvm_coalesced_mmio' object, wherein write indices 'ring->first' and 'ring->last' value could be supplied by a host user-space process. An unprivileged host user or process with access to '/dev/kvm' device could use this flaw to crash the host kernel, resulting in a denial of service or potentially escalating privileges on the system.
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-abi-whitelists-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:python3-perf-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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A heap overflow flaw was found in the Linux kernel's Marvell WiFi chip driver. The vulnerability allows a remote attacker to cause a system crash, resulting in a denial of service, or execute arbitrary code. The highest threat with this vulnerability is with the availability of the system. If code execution occurs, the code will run with the permissions of root. This will affect both confidentiality and integrity of files on the system.
| Product | Identifier | Version | Remediation |
|---|---|---|---|
| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:bpftool-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.src | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-abi-whitelists-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-core-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-devel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-extra-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debug-modules-extra-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-common-ppc64le-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-debuginfo-common-x86_64-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-devel-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-doc-0:4.18.0-80.15.1.el8_0.noarch | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-modules-extra-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:kernel-tools-libs-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-debuginfo-0:4.18.0-80.15.1.el8_0.ppc64le | — |
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| Unresolved product id: BaseOS-8.0.0.Z.E4S:perf-debuginfo-0:4.18.0-80.15.1.el8_0.x86_64 | — |
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{
"acknowledgments": [
{
"names": [
"Intel"
]
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{
"names": [
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"summary": "Acknowledged by upstream."
}
],
"cve": "CVE-2018-12207",
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"id": "CWE-226",
"name": "Sensitive Information in Resource Not Removed Before Reuse"
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"discovery_date": "2018-11-06T00:00:00+00:00",
"ids": [
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"system_name": "Red Hat Bugzilla ID",
"text": "1646768"
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{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle inconsistency between, virtual to physical memory address translations in CPU\u0027s local cache and system software\u0027s Paging structure entries. A privileged guest user may use this flaw to induce a hardware Machine Check Error on the host processor, resulting in a severe DoS scenario by halting the processor.\r\n\r\nSystem software like OS OR Virtual Machine Monitor (VMM) use virtual memory system for storing program instructions and data in memory. Virtual Memory system uses Paging structures like Page Tables and Page Directories to manage system memory. The processor\u0027s Memory Management Unit (MMU) uses Paging structure entries to translate program\u0027s virtual memory addresses to physical memory addresses. The processor stores these address translations into its local cache buffer called - Translation Lookaside Buffer (TLB). TLB has two parts, one for instructions and other for data addresses.\r\n\r\nSystem software can modify its Paging structure entries to change address mappings OR certain attributes like page size etc. Upon such Paging structure alterations in memory, system software must invalidate the corresponding address translations in the processor\u0027s TLB cache. But before this TLB invalidation takes place, a privileged guest user may trigger an instruction fetch operation, which could use an already cached, but now invalid, virtual to physical address translation from Instruction TLB (ITLB). Thus accessing an invalid physical memory address and resulting in halting the processor due to the Machine Check Error (MCE) on Page Size Change.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Machine Check Error on Page Size Change (IFU)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
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"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2018-12207"
},
{
"category": "external",
"summary": "RHBZ#1646768",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1646768"
},
{
"category": "external",
"summary": "RHSB-ifu-page-mce",
"url": "https://access.redhat.com/security/vulnerabilities/ifu-page-mce"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2018-12207",
"url": "https://www.cve.org/CVERecord?id=CVE-2018-12207"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2018-12207"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00210.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2020-01-22T21:26:18+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"url": "https://access.redhat.com/errata/RHSA-2020:0204"
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{
"category": "workaround",
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"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
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"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "hw: Machine Check Error on Page Size Change (IFU)"
},
{
"acknowledgments": [
{
"names": [
"Evgenii Shatokhin",
"Vasily Averin"
],
"organization": "Virtuozzo"
}
],
"cve": "CVE-2018-16884",
"cwe": {
"id": "CWE-416",
"name": "Use After Free"
},
"discovery_date": "2018-12-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1660375"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the Linux kernel\u0027s NFS41+ subsystem. NFS41+ shares mounted in different network namespaces at the same time can make bc_svc_process() use wrong back-channel IDs and cause a use-after-free vulnerability. Thus a malicious container user can cause a host kernel memory corruption and a system panic. Due to the nature of the flaw, privilege escalation cannot be fully ruled out.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "kernel: nfs: use-after-free in svc_process_common()",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
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"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2018-16884"
},
{
"category": "external",
"summary": "RHBZ#1660375",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1660375"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2018-16884",
"url": "https://www.cve.org/CVERecord?id=CVE-2018-16884"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2018-16884",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2018-16884"
}
],
"release_date": "2018-11-27T00:00:00+00:00",
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{
"category": "vendor_fix",
"date": "2020-01-22T21:26:18+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"userInteraction": "NONE",
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{
"category": "impact",
"details": "Important"
}
],
"title": "kernel: nfs: use-after-free in svc_process_common()"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-0154",
"cwe": {
"id": "CWE-284",
"name": "Improper Access Control"
},
"discovery_date": "2019-06-27T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1724393"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "Intel plans to release BIOS firmware to correct this issue. Red Hat\u0027s kernel update should mitigate this vulnerability. Some older hardware will not have BIOS firmware update and will rely on operating system level protection to prevent access while the device is in low-power states. For more information see https://access.redhat.com/solutions/i915-graphics",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-0154"
},
{
"category": "external",
"summary": "RHBZ#1724393",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1724393"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-0154",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-0154"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-0154"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/i915-graphics",
"url": "https://access.redhat.com/solutions/i915-graphics"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2020-01-22T21:26:18+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"url": "https://access.redhat.com/errata/RHSA-2020:0204"
},
{
"category": "workaround",
"details": "Preventing loading of the i915 kernel module will prevent attackers from using this exploit against the system however the power management functionality of the card will be disabled and the system may draw additional power. See this KCS article (https://access.redhat.com/solutions/41278) for instructions on how to disable a kernel module. Graphical displays may also be at low resolution or not work correctly. This mitigation may not be suitable if running graphical tools locally is required.",
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"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
},
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"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: Intel GPU Denial Of Service while accessing MMIO in lower power state"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-0155",
"cwe": {
"id": "CWE-284",
"name": "Improper Access Control"
},
"discovery_date": "2019-06-27T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1724398"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the Intel graphics hardware (GPU), where a local attacker with the ability to issue commands to the GPU could inadvertently lead to memory corruption and possible privilege escalation. The attacker could use the GPU blitter to perform privilege MMIO operations, not limited to the address space required to function correctly.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: Intel GPU blitter manipulation can allow for arbitrary kernel memory write",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "Red Hat Product Security is aware of this issue. Updates will be released as they become available. For additional information, please refer to the Red Hat Knowledgebase article: https://access.redhat.com/solutions/i915-graphics",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-0155"
},
{
"category": "external",
"summary": "RHBZ#1724398",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1724398"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-0155",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-0155"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-0155",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-0155"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/i915-graphics",
"url": "https://access.redhat.com/solutions/i915-graphics"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00242.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00242.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2020-01-22T21:26:18+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"url": "https://access.redhat.com/errata/RHSA-2020:0204"
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{
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"details": "Preventing loading of the i915 kernel module will prevent attackers from using this exploit against the system however the power management functionality of the card will be disabled and the system may draw additional power. See this KCS article( https://access.redhat.com/solutions/41278 ) for instructions on how to disable a kernel module. Graphical displays may also be at low resolution or not work correctly. This mitigation may not be suitable if running graphical tools locally is required.",
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{
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"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 8.8,
"baseSeverity": "HIGH",
"confidentialityImpact": "HIGH",
"integrityImpact": "HIGH",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H",
"version": "3.0"
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"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "hw: Intel GPU blitter manipulation can allow for arbitrary kernel memory write"
},
{
"acknowledgments": [
{
"names": [
"Jason Wang"
],
"organization": "Red Hat Inc.",
"summary": "This issue was discovered by Red Hat."
}
],
"cve": "CVE-2019-3900",
"cwe": {
"id": "CWE-835",
"name": "Loop with Unreachable Exit Condition (\u0027Infinite Loop\u0027)"
},
"discovery_date": "2019-04-10T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1698757"
}
],
"notes": [
{
"category": "description",
"text": "An infinite loop issue was found in the vhost_net kernel module while handling incoming packets in handle_rx(). The infinite loop could occur if one end sends packets faster than the other end can process them. A guest user, maybe a remote one, could use this flaw to stall the vhost_net kernel thread, resulting in a DoS scenario.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "Kernel: vhost_net: infinite loop while receiving packets leads to DoS",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "This issue does not affect the versions of the kernel package as shipped with Red Hat Enterprise Linux 5 and Red Hat Enterprise MRG 2.\n\nThis issue affects the version of Linux kernel as shipped with Red Hat Enterprise Linux 6 and 7. Future kernel updates for Red Hat Enterprise Linux 6 and 7 may address this issue.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-3900"
},
{
"category": "external",
"summary": "RHBZ#1698757",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1698757"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-3900",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-3900"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-3900",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-3900"
}
],
"release_date": "2019-04-25T00:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2020-01-22T21:26:18+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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{
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"attackComplexity": "HIGH",
"attackVector": "NETWORK",
"availabilityImpact": "HIGH",
"baseScore": 6.3,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "NONE",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:N/AC:H/PR:L/UI:N/S:C/C:N/I:N/A:H",
"version": "3.0"
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"details": "Important"
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],
"title": "Kernel: vhost_net: infinite loop while receiving packets leads to DoS"
},
{
"cve": "CVE-2019-5489",
"cwe": {
"id": "CWE-200",
"name": "Exposure of Sensitive Information to an Unauthorized Actor"
},
"discovery_date": "2019-01-07T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1664110"
}
],
"notes": [
{
"category": "description",
"text": "A new software page cache side channel attack scenario was discovered in operating systems that implement the very common \u0027page cache\u0027 caching mechanism. A malicious user/process could use \u0027in memory\u0027 page-cache knowledge to infer access timings to shared memory and gain knowledge which can be used to reduce effectiveness of cryptographic strength by monitoring algorithmic behavior, infer access patterns of memory to determine code paths taken, and exfiltrate data to a blinded attacker through page-granularity access times as a side-channel.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "Kernel: page cache side channel attacks",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-5489"
},
{
"category": "external",
"summary": "RHBZ#1664110",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1664110"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-5489",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-5489"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-5489",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-5489"
}
],
"release_date": "2019-01-06T00:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2020-01-22T21:26:18+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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{
"cvss_v3": {
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"attackVector": "NETWORK",
"availabilityImpact": "NONE",
"baseScore": 7.1,
"baseSeverity": "HIGH",
"confidentialityImpact": "HIGH",
"integrityImpact": "LOW",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:N/AC:H/PR:L/UI:N/S:C/C:H/I:L/A:N",
"version": "3.0"
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{
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"details": "Important"
}
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"title": "Kernel: page cache side channel attacks"
},
{
"cve": "CVE-2019-9506",
"cwe": {
"id": "CWE-327",
"name": "Use of a Broken or Risky Cryptographic Algorithm"
},
"discovery_date": "2019-06-11T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1727857"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was discovered in the Bluetooth protocol. An attacker within physical proximity to the Bluetooth connection could downgrade the encryption protocol to be trivially brute forced.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hardware: bluetooth: BR/EDR encryption key negotiation attacks (KNOB)",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-9506"
},
{
"category": "external",
"summary": "RHBZ#1727857",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1727857"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-9506",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-9506"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-9506",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-9506"
}
],
"release_date": "2019-08-10T09:00:00+00:00",
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{
"category": "vendor_fix",
"date": "2020-01-22T21:26:18+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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},
"url": "https://access.redhat.com/errata/RHSA-2020:0204"
},
{
"category": "workaround",
"details": "At this time there is no known mitigation if bluetooth hardware is to be continue to be used. Replacing the hardware with its wired version and disabling bluetooth may be a suitable alternative for some environments.",
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"attackVector": "NETWORK",
"availabilityImpact": "LOW",
"baseScore": 7.0,
"baseSeverity": "HIGH",
"confidentialityImpact": "HIGH",
"integrityImpact": "LOW",
"privilegesRequired": "NONE",
"scope": "UNCHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:N/AC:H/PR:N/UI:N/S:U/C:H/I:L/A:L",
"version": "3.0"
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"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "hardware: bluetooth: BR/EDR encryption key negotiation attacks (KNOB)"
},
{
"acknowledgments": [
{
"names": [
"huangwen"
],
"organization": "ADLab of Venustech"
}
],
"cve": "CVE-2019-10126",
"cwe": {
"id": "CWE-122",
"name": "Heap-based Buffer Overflow"
},
"discovery_date": "2019-05-30T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1716992"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the mwifiex implementation in the Linux kernel. A system connecting to wireless access point could be manipulated by an attacker with advanced permissions on the access point into localized memory corruption or possibly privilege escalation.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "kernel: Heap overflow in mwifiex_uap_parse_tail_ies function in drivers/net/wireless/marvell/mwifiex/ie.c",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-10126"
},
{
"category": "external",
"summary": "RHBZ#1716992",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1716992"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-10126",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-10126"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-10126",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-10126"
}
],
"release_date": "2019-05-31T00:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2020-01-22T21:26:18+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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{
"category": "impact",
"details": "Important"
}
],
"title": "kernel: Heap overflow in mwifiex_uap_parse_tail_ies function in drivers/net/wireless/marvell/mwifiex/ie.c"
},
{
"acknowledgments": [
{
"names": [
"Intel"
]
}
],
"cve": "CVE-2019-11135",
"cwe": {
"id": "CWE-385",
"name": "Covert Timing Channel"
},
"discovery_date": "2019-09-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1753062"
}
],
"notes": [
{
"category": "description",
"text": "A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing.\r\n\r\nIntel\u0027s Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. The CPU executes instructions in the critical-sections as transactions, while ensuring their atomic state. When such transaction execution is unsuccessful, the processor cannot ensure atomic updates to the transaction memory, so the processor rolls back or aborts such transaction execution.\r\n\r\nWhile TSX Asynchronous Abort (TAA) is pending, CPU may continue to read data from architectural buffers and pass it to the dependent speculative operations. This may cause information leakage via speculative side-channel means, which is quite similar to the Microarchitectural Data Sampling (MDS) issue.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "hw: TSX Transaction Asynchronous Abort (TAA)",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "libvirt and qemu-kvm on Red Hat Enterprise Linux 6 are not affected by this vulnerability as they do not support MSR-based CPU features.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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"url": "https://www.cve.org/CVERecord?id=CVE-2019-11135"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-11135"
},
{
"category": "external",
"summary": "https://access.redhat.com/solutions/tsx-asynchronousabort",
"url": "https://access.redhat.com/solutions/tsx-asynchronousabort"
},
{
"category": "external",
"summary": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html",
"url": "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00270.html"
}
],
"release_date": "2019-11-12T18:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2020-01-22T21:26:18+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"attackComplexity": "LOW",
"attackVector": "LOCAL",
"availabilityImpact": "NONE",
"baseScore": 6.5,
"baseSeverity": "MEDIUM",
"confidentialityImpact": "HIGH",
"integrityImpact": "NONE",
"privilegesRequired": "LOW",
"scope": "CHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N",
"version": "3.0"
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"threats": [
{
"category": "impact",
"details": "Moderate"
}
],
"title": "hw: TSX Transaction Asynchronous Abort (TAA)"
},
{
"acknowledgments": [
{
"names": [
"Huangwen"
],
"organization": "ADLab of Venustech"
}
],
"cve": "CVE-2019-14816",
"cwe": {
"id": "CWE-122",
"name": "Heap-based Buffer Overflow"
},
"discovery_date": "2019-08-21T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1744149"
}
],
"notes": [
{
"category": "description",
"text": "A vulnerability was found in the Linux kernel\u0027s Marvell WiFi chip driver. Where, while parsing vendor-specific informational attributes, an attacker on the same WiFi physical network segment could cause a system crash, resulting in a denial of service, or potentially execute arbitrary code. This flaw affects the network interface at the most basic level meaning the attacker only needs to affiliate with the same network device as the vulnerable system to create an attack path.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "kernel: heap overflow in mwifiex_update_vs_ie() function of Marvell WiFi driver",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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},
"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-14816"
},
{
"category": "external",
"summary": "RHBZ#1744149",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1744149"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-14816",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-14816"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-14816",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-14816"
},
{
"category": "external",
"summary": "https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7caac62ed598a196d6ddf8d9c121e12e082cac3a",
"url": "https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7caac62ed598a196d6ddf8d9c121e12e082cac3a"
}
],
"release_date": "2019-08-28T10:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2020-01-22T21:26:18+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"url": "https://access.redhat.com/errata/RHSA-2020:0204"
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{
"category": "workaround",
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"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "ADJACENT_NETWORK",
"availabilityImpact": "HIGH",
"baseScore": 8.0,
"baseSeverity": "HIGH",
"confidentialityImpact": "HIGH",
"integrityImpact": "HIGH",
"privilegesRequired": "LOW",
"scope": "UNCHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:A/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H",
"version": "3.0"
},
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"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "kernel: heap overflow in mwifiex_update_vs_ie() function of Marvell WiFi driver"
},
{
"acknowledgments": [
{
"names": [
"Matt Delco"
],
"organization": "Google.com"
}
],
"cve": "CVE-2019-14821",
"cwe": {
"id": "CWE-787",
"name": "Out-of-bounds Write"
},
"discovery_date": "2019-08-28T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1746708"
}
],
"notes": [
{
"category": "description",
"text": "An out-of-bounds access issue was found in the way Linux kernel\u0027s KVM hypervisor implements the Coalesced MMIO write operation. It operates on an MMIO ring buffer \u0027struct kvm_coalesced_mmio\u0027 object, wherein write indices \u0027ring-\u003efirst\u0027 and \u0027ring-\u003elast\u0027 value could be supplied by a host user-space process. An unprivileged host user or process with access to \u0027/dev/kvm\u0027 device could use this flaw to crash the host kernel, resulting in a denial of service or potentially escalating privileges on the system.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "Kernel: KVM: OOB memory access via mmio ring buffer",
"title": "Vulnerability summary"
},
{
"category": "other",
"text": "This issue requires unprivileged users to have access to \u0027/dev/kvm\u0027 device. So restricting access to \u0027/dev/kvm\u0027 device to known trusted users could limit its exploitation by untrusted users/processes.",
"title": "Statement"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
"product_status": {
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"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-14821"
},
{
"category": "external",
"summary": "RHBZ#1746708",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1746708"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-14821",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-14821"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-14821",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-14821"
}
],
"release_date": "2019-09-17T17:00:00+00:00",
"remediations": [
{
"category": "vendor_fix",
"date": "2020-01-22T21:26:18+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"attackVector": "LOCAL",
"availabilityImpact": "HIGH",
"baseScore": 7.0,
"baseSeverity": "HIGH",
"confidentialityImpact": "HIGH",
"integrityImpact": "HIGH",
"privilegesRequired": "LOW",
"scope": "UNCHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:L/AC:H/PR:L/UI:N/S:U/C:H/I:H/A:H",
"version": "3.0"
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"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "Kernel: KVM: OOB memory access via mmio ring buffer"
},
{
"acknowledgments": [
{
"names": [
"Huangwen and Wang Qize"
],
"organization": "ADLab of VenusTech"
}
],
"cve": "CVE-2019-14901",
"cwe": {
"id": "CWE-805",
"name": "Buffer Access with Incorrect Length Value"
},
"discovery_date": "2019-11-18T00:00:00+00:00",
"ids": [
{
"system_name": "Red Hat Bugzilla ID",
"text": "1773519"
}
],
"notes": [
{
"category": "description",
"text": "A heap overflow flaw was found in the Linux kernel\u0027s Marvell WiFi chip driver. The vulnerability allows a remote attacker to cause a system crash, resulting in a denial of service, or execute arbitrary code. The highest threat with this vulnerability is with the availability of the system. If code execution occurs, the code will run with the permissions of root. This will affect both confidentiality and integrity of files on the system.",
"title": "Vulnerability description"
},
{
"category": "summary",
"text": "kernel: heap overflow in marvell/mwifiex/tdls.c",
"title": "Vulnerability summary"
},
{
"category": "general",
"text": "The CVSS score(s) listed for this vulnerability do not reflect the associated product\u0027s status, and are included for informational purposes to better understand the severity of this vulnerability.",
"title": "CVSS score applicability"
}
],
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"references": [
{
"category": "self",
"summary": "Canonical URL",
"url": "https://access.redhat.com/security/cve/CVE-2019-14901"
},
{
"category": "external",
"summary": "RHBZ#1773519",
"url": "https://bugzilla.redhat.com/show_bug.cgi?id=1773519"
},
{
"category": "external",
"summary": "https://www.cve.org/CVERecord?id=CVE-2019-14901",
"url": "https://www.cve.org/CVERecord?id=CVE-2019-14901"
},
{
"category": "external",
"summary": "https://nvd.nist.gov/vuln/detail/CVE-2019-14901",
"url": "https://nvd.nist.gov/vuln/detail/CVE-2019-14901"
}
],
"release_date": "2019-11-22T00:00:00+00:00",
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{
"category": "vendor_fix",
"date": "2020-01-22T21:26:18+00:00",
"details": "For details on how to apply this update, which includes the changes described in this advisory, refer to:\n\nhttps://access.redhat.com/articles/11258\n\nThe system must be rebooted for this update to take effect.",
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"restart_required": {
"category": "machine"
},
"url": "https://access.redhat.com/errata/RHSA-2020:0204"
}
],
"scores": [
{
"cvss_v3": {
"attackComplexity": "LOW",
"attackVector": "ADJACENT_NETWORK",
"availabilityImpact": "HIGH",
"baseScore": 8.8,
"baseSeverity": "HIGH",
"confidentialityImpact": "HIGH",
"integrityImpact": "HIGH",
"privilegesRequired": "NONE",
"scope": "UNCHANGED",
"userInteraction": "NONE",
"vectorString": "CVSS:3.0/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:H/A:H",
"version": "3.0"
},
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]
}
],
"threats": [
{
"category": "impact",
"details": "Important"
}
],
"title": "kernel: heap overflow in marvell/mwifiex/tdls.c"
}
]
}
Sightings
| Author | Source | Type | Date | Other |
|---|
Nomenclature
- Seen: The vulnerability was mentioned, discussed, or observed by the user.
- Confirmed: The vulnerability has been validated from an analyst's perspective.
- Published Proof of Concept: A public proof of concept is available for this vulnerability.
- Exploited: The vulnerability was observed as exploited by the user who reported the sighting.
- Patched: The vulnerability was observed as successfully patched by the user who reported the sighting.
- Not exploited: The vulnerability was not observed as exploited by the user who reported the sighting.
- Not confirmed: The user expressed doubt about the validity of the vulnerability.
- Not patched: The vulnerability was not observed as successfully patched by the user who reported the sighting.