CVE-2026-74674 (GCVE-0-2026-74674)

Vulnerability from cvelistv5 – Published: 2026-08-22 15:32 – Updated: 2026-08-25 05:41
VLAI
Title
mm: fix incorrect flush address in direct page table reclaim
Summary
In the Linux kernel, the following vulnerability has been resolved: mm: fix incorrect flush address in direct page table reclaim When zap_pte_range reclaims a page table, it does: pte_free_tlb(tlb, pmd_pgtable(pmdval), addr); and this is unconditionally wrong: if this code executes, addr *always* points one past the end of the range covered by the table. The addr parameter is used to flush the TLB (really the paging-structure-cache) to drop references to the to-be-freed table, and any architecture that cares about the parameter will flush the wrong address. (But they'll still free the correct page). I think it's worth contemplating why the kernel works at all. If we hit the offending line of code, we will first clear the PMD entry (line 1954, zap_empty_pte_table), then we will issue pending flushes if force_flush is set (tlb_flush_mmu_tlbonly(tlb)), then we will skip the retry on line 1979 (phew!), and then we will do the offending pte_free_tlb call. *Or* we will clear the PMD entry immediately before pte_free_tlb (line 1983, zap_pte_table_if_empty). If we have any pending flushes (i.e. we actually zapped any last-level entries) at the time we clear the PMD entry, then the flush really ought to flush all references to the table (Linus certainly seems to think it will on all architectures [0]). The condition under which we have no accumulated flushes at the time of the clear is very complex (the whole zap_pte_range function has absurdly complex control flow). If we do hit the bad case, then we will end up clearing the PMD entry after the last time the range is flushed, and any CPU is free to cache a reference to the (empty) page table. If this happens due to an ordinary read or write, it would segfault, so it would be rare. But the cache could be speculatively filled as well. Then we'll flush the wrong address and then free and possibly reuse the table. On x86, even flushing the wrong address works on non-KPTI Intel systems because INVLPG flushes *all* paging-structure-caches, not just the ones for the target address. But INVPCID does not, and flush_tlb_one_user will use INVPCID if it's available. And then we're toast. AMD systems are more susceptible: we set the EFER.TCE bit, which makes even INVLPG only flush the target address. I think this might fix an issue in ripgrep reported here: https://github.com/BurntSushi/ripgrep/issues/3494 [0] https://lore.kernel.org/all/CA+55aFzBggoXtNXQeng5d_mRoDnaMBE5Y+URs+PHR67nUpMtaw@mail.gmail.com/T/#u
Severity
7.8 (High)
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H
Assigner
Linux CNA under the mitre root
CNA scorecard D 53/100 over 6666 records in the last 180 days details
References
Impacted products
Vendor Product Version CPE status
Linux Linux Affected: 4c640eb4181cf8de74c8b9e7c9cf16bf8d26b73e , < 0b8ff21cbda8808c86b18f1b0ca2d0025af9a80a (git)
Affected: 4c640eb4181cf8de74c8b9e7c9cf16bf8d26b73e , < 478a1c3abebfc717db0d1281a9cdd7befafee542 (git)
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Linux Linux Affected: 7.0
Unaffected: 0 , < 7.0 (semver)
Unaffected: 7.1.9 , ≤ 7.1.* (semver)
Unaffected: 7.2 , ≤ * (original_commit_for_fix)
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Show details on NVD website
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          "lang": "en",
          "value": "In the Linux kernel, the following vulnerability has been resolved:\n\nmm: fix incorrect flush address in direct page table reclaim\n\nWhen zap_pte_range reclaims a page table, it does:\n\n    pte_free_tlb(tlb, pmd_pgtable(pmdval), addr);\n\nand this is unconditionally wrong: if this code executes, addr *always*\npoints one past the end of the range covered by the table.  The addr\nparameter is used to flush the TLB (really the paging-structure-cache)\nto drop references to the to-be-freed table, and any architecture that\ncares about the parameter will flush the wrong address.  (But they\u0027ll\nstill free the correct page).\n\nI think it\u0027s worth contemplating why the kernel works at all.\n\nIf we hit the offending line of code, we will first clear the PMD entry\n(line 1954, zap_empty_pte_table), then we will issue pending flushes if\nforce_flush is set (tlb_flush_mmu_tlbonly(tlb)), then we will skip the\nretry on line 1979 (phew!), and then we will do the offending\npte_free_tlb call.  *Or* we will clear the PMD entry immediately before\npte_free_tlb (line 1983, zap_pte_table_if_empty).\n\nIf we have any pending flushes (i.e. we actually zapped any last-level\nentries) at the time we clear the PMD entry, then the flush really ought\nto flush all references to the table (Linus certainly seems to think it\nwill on all architectures [0]).\n\nThe condition under which we have no accumulated flushes at the time of\nthe clear is very complex (the whole zap_pte_range function has absurdly\ncomplex control flow).  If we do hit the bad case, then we will end up\nclearing the PMD entry after the last time the range is flushed, and any\nCPU is free to cache a reference to the (empty) page table.  If this\nhappens due to an ordinary read or write, it would segfault, so it would\nbe rare.  But the cache could be speculatively filled as well.  Then\nwe\u0027ll flush the wrong address and then free and possibly reuse the\ntable.\n\nOn x86, even flushing the wrong address works on non-KPTI Intel systems\nbecause INVLPG flushes *all* paging-structure-caches, not just the ones\nfor the target address.  But INVPCID does not, and flush_tlb_one_user\nwill use INVPCID if it\u0027s available.  And then we\u0027re toast.  AMD systems\nare more susceptible: we set the EFER.TCE bit, which makes even INVLPG\nonly flush the target address.\n\nI think this might fix an issue in ripgrep reported here:\nhttps://github.com/BurntSushi/ripgrep/issues/3494\n\n[0] https://lore.kernel.org/all/CA+55aFzBggoXtNXQeng5d_mRoDnaMBE5Y+URs+PHR67nUpMtaw@mail.gmail.com/T/#u"
        }
      ],
      "metrics": [
        {
          "cvssV3_1": {
            "baseScore": 7.8,
            "baseSeverity": "HIGH",
            "vectorString": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H",
            "version": "3.1"
          },
          "scenarios": [
            {
              "lang": "en",
              "value": "AV:L - The bug is only reachable via local memory-management syscalls\u2014primarily madvise(MADV_DONTNEED) on anonymous mappings\u2014that drive zap_pte_range() page-table reclaim; there is no network, adjacent-radio, or physical-device path to this code.\nAC:L - An unprivileged attacker can repeatedly mmap and madvise(DONTNEED) 2MB+ anonymous regions and run concurrent memory pressure (as in the ripgrep repro) to hit the faulty pte_free_tlb() flush; attacker-controlled syscalls and threading make triggering the bad case feasible rather than dependent on uncontrollable system state.\nPR:L - Exploitation requires only a local unprivileged user manipulating their own address space through standard madvise/mmap syscalls; no root, capabilities beyond normal UID, or authentication is needed, and this works within user namespaces on the caller\u0027s mm.\nUI:N - No victim interaction is required; the attacker directly issues the syscalls and memory-access patterns that cause incorrect paging-structure-cache flushes during PTE page reclaim.\nS:U - Impact is stale paging-structure-cache entries and corrupted virtual-to-physical translations within the attacker\u0027s process and kernel MM subsystem\u2014standard local memory corruption, not a VM escape, IOMMU bypass, or cross-authority sandbox breakout.\nC:H - Flushing the wrong address leaves CPUs with cached references to freed PTE pages; once reused, stale translations can map unrelated physical pages into the attacker\u0027s address space, giving arbitrary read primitives and information disclosure consistent with use-after-free severity.\nI:H - Freed page-table pages can be reallocated while stale paging-structure caches still reference them, enabling wrong virtual-to-physical mappings and demonstrated user-space memory corruption (ripgrep/musl heap corruption), exploitable for arbitrary writes and control-flow hijacking.\nA:H - Stale TLB/paging-structure-cache entries after incorrect flushes cause user-space SIGSEGV (demonstrated in ripgrep on Linux 7.0) and can destabilize or crash affected workloads; memory-corruption class bugs in the MM path carry high availability impact even when not fully weaponized."
            }
          ]
        }
      ],
      "providerMetadata": {
        "dateUpdated": "2026-08-25T05:41:26.569Z",
        "orgId": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
        "shortName": "Linux"
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      "references": [
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          "url": "https://git.kernel.org/stable/c/0b8ff21cbda8808c86b18f1b0ca2d0025af9a80a"
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        {
          "url": "https://git.kernel.org/stable/c/478a1c3abebfc717db0d1281a9cdd7befafee542"
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      "title": "mm: fix incorrect flush address in direct page table reclaim",
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    "assignerShortName": "Linux",
    "cveId": "CVE-2026-74674",
    "datePublished": "2026-08-22T15:32:43.670Z",
    "dateReserved": "2026-08-15T05:44:03.925Z",
    "dateUpdated": "2026-08-25T05:41:26.569Z",
    "state": "PUBLISHED"
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      "date": "2026-10-16",
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                "product": "Linux",
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              }
            ],
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        "cveTags": [],
        "descriptions": [
          {
            "lang": "en",
            "value": "In the Linux kernel, the following vulnerability has been resolved:\n\nmm: fix incorrect flush address in direct page table reclaim\n\nWhen zap_pte_range reclaims a page table, it does:\n\n    pte_free_tlb(tlb, pmd_pgtable(pmdval), addr);\n\nand this is unconditionally wrong: if this code executes, addr *always*\npoints one past the end of the range covered by the table.  The addr\nparameter is used to flush the TLB (really the paging-structure-cache)\nto drop references to the to-be-freed table, and any architecture that\ncares about the parameter will flush the wrong address.  (But they\u0027ll\nstill free the correct page).\n\nI think it\u0027s worth contemplating why the kernel works at all.\n\nIf we hit the offending line of code, we will first clear the PMD entry\n(line 1954, zap_empty_pte_table), then we will issue pending flushes if\nforce_flush is set (tlb_flush_mmu_tlbonly(tlb)), then we will skip the\nretry on line 1979 (phew!), and then we will do the offending\npte_free_tlb call.  *Or* we will clear the PMD entry immediately before\npte_free_tlb (line 1983, zap_pte_table_if_empty).\n\nIf we have any pending flushes (i.e. we actually zapped any last-level\nentries) at the time we clear the PMD entry, then the flush really ought\nto flush all references to the table (Linus certainly seems to think it\nwill on all architectures [0]).\n\nThe condition under which we have no accumulated flushes at the time of\nthe clear is very complex (the whole zap_pte_range function has absurdly\ncomplex control flow).  If we do hit the bad case, then we will end up\nclearing the PMD entry after the last time the range is flushed, and any\nCPU is free to cache a reference to the (empty) page table.  If this\nhappens due to an ordinary read or write, it would segfault, so it would\nbe rare.  But the cache could be speculatively filled as well.  Then\nwe\u0027ll flush the wrong address and then free and possibly reuse the\ntable.\n\nOn x86, even flushing the wrong address works on non-KPTI Intel systems\nbecause INVLPG flushes *all* paging-structure-caches, not just the ones\nfor the target address.  But INVPCID does not, and flush_tlb_one_user\nwill use INVPCID if it\u0027s available.  And then we\u0027re toast.  AMD systems\nare more susceptible: we set the EFER.TCE bit, which makes even INVLPG\nonly flush the target address.\n\nI think this might fix an issue in ripgrep reported here:\nhttps://github.com/BurntSushi/ripgrep/issues/3494\n\n[0] https://lore.kernel.org/all/CA+55aFzBggoXtNXQeng5d_mRoDnaMBE5Y+URs+PHR67nUpMtaw@mail.gmail.com/T/#u"
          },
          {
            "lang": "es",
            "value": "En el kernel de Linux, la siguiente vulnerabilidad ha sido resuelta:\n\nmm: corrige direcci\u00f3n de vaciado incorrecta en la recuperaci\u00f3n directa de tablas de p\u00e1ginas\n\nCuando zap_pte_range recupera una tabla de p\u00e1ginas, hace lo siguiente:\n\n    pte_free_tlb(tlb, pmd_pgtable(pmdval), addr);\n\ny esto es incondicionalmente incorrecto: si este c\u00f3digo se ejecuta, addr siempre apunta uno m\u00e1s all\u00e1 del final del rango cubierto por la tabla. El par\u00e1metro addr se utiliza para vaciar la TLB (en realidad, la cach\u00e9 de estructura de paginaci\u00f3n) para eliminar referencias a la tabla que se va a liberar, y cualquier arquitectura que se preocupe por el par\u00e1metro vaciar\u00e1 la direcci\u00f3n incorrecta. (Pero seguir\u00e1n liberando la p\u00e1gina correcta).\n\nCreo que vale la pena contemplar por qu\u00e9 el kernel funciona en absoluto.\n\nSi llegamos a la l\u00ednea de c\u00f3digo ofensiva, primero borraremos la entrada PMD (l\u00ednea 1954, zap_empty_pte_table), luego emitiremos vaciados pendientes si force_flush est\u00e1 establecido (tlb_flush_mmu_tlbonly(tlb)), luego omitiremos el reintento en la l\u00ednea 1979 (\u00a1uf!), y luego haremos la llamada ofensiva a pte_free_tlb. O borraremos la entrada PMD inmediatamente antes de pte_free_tlb (l\u00ednea 1983, zap_pte_table_if_empty).\n\nSi tenemos alg\u00fan vaciado pendiente (es decir, si realmente eliminamos alguna entrada de \u00faltimo nivel) en el momento en que borramos la entrada PMD, entonces el vaciado realmente deber\u00eda vaciar todas las referencias a la tabla (Linus ciertamente parece pensar que lo har\u00e1 en todas las arquitecturas [0]).\n\nLa condici\u00f3n bajo la cual no tenemos vaciados acumulados en el momento del borrado es muy compleja (toda la funci\u00f3n zap_pte_range tiene un flujo de control absurdamente complejo). Si llegamos al caso problem\u00e1tico, terminaremos borrando la entrada PMD despu\u00e9s de la \u00faltima vez que se vac\u00eda el rango, y cualquier CPU es libre de almacenar en cach\u00e9 una referencia a la tabla de p\u00e1ginas (vac\u00eda). Si esto sucede debido a una lectura o escritura ordinaria, causar\u00eda un segfault, por lo que ser\u00eda raro. Pero la cach\u00e9 tambi\u00e9n podr\u00eda llenarse de forma especulativa. Luego vaciaremos la direcci\u00f3n incorrecta y luego liberaremos y posiblemente reutilizaremos la tabla.\n\nEn x86, incluso vaciar la direcci\u00f3n incorrecta funciona en sistemas Intel sin KPTI porque INVLPG vac\u00eda todas las cach\u00e9s de estructura de paginaci\u00f3n, no solo las de la direcci\u00f3n de destino. Pero INVPCID no lo hace, y flush_tlb_one_user usar\u00e1 INVPCID si est\u00e1 disponible. Y entonces estamos perdidos. Los sistemas AMD son m\u00e1s susceptibles: configuramos el bit EFER.TCE, lo que hace que incluso INVLPG solo vac\u00ede la direcci\u00f3n de destino.\n\nCreo que esto podr\u00eda solucionar un problema en ripgrep reportado aqu\u00ed:\nhttps://github.com/BurntSushi/ripgrep/issues/3494\n\n[0] https://lore.kernel.org/all/CA+55aFzBggoXtNXQeng5d_mRoDnaMBE5Y+URs+PHR67nUpMtaw@mail.gmail.com/T/#u"
          }
        ],
        "id": "CVE-2026-74674",
        "lastModified": "2026-10-14T13:10:00.187",
        "metrics": {
          "cvssMetricV31": [
            {
              "cvssData": {
                "attackComplexity": "LOW",
                "attackVector": "LOCAL",
                "availabilityImpact": "HIGH",
                "baseScore": 7.8,
                "baseSeverity": "HIGH",
                "confidentialityImpact": "HIGH",
                "integrityImpact": "HIGH",
                "privilegesRequired": "LOW",
                "scope": "UNCHANGED",
                "userInteraction": "NONE",
                "vectorString": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H",
                "version": "3.1"
              },
              "exploitabilityScore": 1.8,
              "impactScore": 5.9,
              "source": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
              "type": "Secondary"
            }
          ]
        },
        "published": "2026-08-22T16:16:41.480",
        "references": [
          {
            "source": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
            "url": "https://git.kernel.org/stable/c/0b8ff21cbda8808c86b18f1b0ca2d0025af9a80a"
          },
          {
            "source": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
            "url": "https://git.kernel.org/stable/c/478a1c3abebfc717db0d1281a9cdd7befafee542"
          }
        ],
        "sourceIdentifier": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
        "vulnStatus": "Received"
      }
    },
    "redhat_vex": {
      "aggregate_severity": "Moderate",
      "current_release_date": "2026-08-25T08:54:04+00:00",
      "cve": "CVE-2026-74674",
      "id": "CVE-2026-74674",
      "initial_release_date": "2026-08-22T00:00:00+00:00",
      "product_status:known_affected": "14",
      "product_status:known_not_affected": "260",
      "source": "Red Hat CSAF VEX",
      "status": "final",
      "title": "kernel: mm: fix incorrect flush address in direct page table reclaim",
      "url": "https://security.access.redhat.com/data/csaf/v2/vex/2026/cve-2026-74674.json",
      "version": "3"
    }
  }
}



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