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6 vulnerabilities found for risc0 by risc0
CVE-2025-61588 (GCVE-0-2025-61588)
Vulnerability from nvd – Published: 2025-10-01 23:30 – Updated: 2025-10-02 18:01
VLAI
Title
risc0 vulnerable to arbitrary code execution in guest via memory safety failure in `sys_read`
Summary
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture. In versions 2.0.2 and below of risc0-zkvm-platform, when the zkVM guest calls sys_read, the host is able to use a crafted response to write to an arbitrary memory location in the guest. This capability can be leveraged to execute arbitrary code within the guest. As sys_read is the mechanism by which input is requested by the guest, all guest programs built with the affected versions are vulnerable. This critically compromises the soundness guarantees of the guest program. Other affected packages include risc0-aggregation versions below 0.9, risc0-zkos-v1compat below 2.1.0, risc0-zkvm versions between 3.0.0-rc.1 and 3.0.1. This issue has been fixed in the following versions: risc0-zkvm-platform 2.1.0, risc0-zkos-v1compat 2.1.0, risc0-aggregation 0.9, and risc0-zkvm 2.3.2 and 3.0.3.
Severity
SSVC
Exploitation: none
Automatable: yes
Technical Impact: total
CISA Coordinator (v2.0.3)
CWE
- CWE-94 - Improper Control of Generation of Code ('Code Injection')
Assigner
References
3 references
| URL | Tags |
|---|---|
| https://github.com/risc0/risc0/security/advisorie… | x_refsource_CONFIRM |
| https://github.com/risc0/risc0/pull/3351 | x_refsource_MISC |
| https://github.com/risc0/risc0/commit/3f00e1fa015… | x_refsource_MISC |
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CVE-2025-54873 (GCVE-0-2025-54873)
Vulnerability from nvd – Published: 2025-08-05 23:35 – Updated: 2025-08-06 13:53
VLAI
Title
RISC Zero Underconstrained Vulnerability: Division
Summary
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture. RISC packages risc0-zkvm versions 2.0.0 through 2.1.0 and risc0-circuit-rv32im and risc0-circuit-rv32im-sys versions 2.0.0 through 2.0.4 contain vulnerabilities where signed integer division allows multiple outputs for certain inputs with only one being valid, and division by zero results are underconstrained. This issue is fixed in risc0-zkvm version 2.2.0 and version 3.0.0 for the risc0-circuit-rv32im and risc0-circuit-rv32im-sys packages.
Severity
SSVC
Exploitation: none
Automatable: yes
Technical Impact: partial
CISA Coordinator (v2.0.3)
CWE
- CWE-369 - Divide By Zero
Assigner
References
3 references
| URL | Tags |
|---|---|
| https://github.com/risc0/risc0/security/advisorie… | x_refsource_CONFIRM |
| https://github.com/risc0/risc0/pull/3235 | x_refsource_MISC |
| https://github.com/risc0/zirgen/pull/249 | x_refsource_MISC |
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CVE-2025-52484 (GCVE-0-2025-52484)
Vulnerability from nvd – Published: 2025-06-20 17:21 – Updated: 2025-06-23 15:28
VLAI
Title
RISC Zero zkVM Underconstrained Vulnerability
Summary
RISC Zero is a general computing platform based on zk-STARKs and the RISC-V microarchitecture. Due to a missing constraint in the rv32im circuit, any 3-register RISC-V instruction (including remu and divu) in risc0-zkvm 2.0.0, 2.0.1, and 2.0.2 are vulnerable to an attack by a malicious prover. The main idea for the attack is to confuse the RISC-V virtual machine into treating the value of the rs1 register as the same as the rs2 register due to a lack of constraints in the rv32im circuit. Rust applications using the risc0-zkvm crate at versions 2.0.0, 2.0.1, and 2.0.2 should upgrade to version 2.1.0. Smart contract applications using the official RISC Zero Verifier Router do not need to take any action: zkVM version 2.1 is active on all official routers, and version 2.0 has been disabled. Smart contract applications not using the verifier router should update their contracts to send verification calls to the 2.1 version of the verifier.
Severity
SSVC
Exploitation: none
Automatable: yes
Technical Impact: partial
CISA Coordinator (v2.0.3)
CWE
- CWE-345 - Insufficient Verification of Data Authenticity
Assigner
References
7 references
| URL | Tags |
|---|---|
| https://github.com/risc0/risc0/security/advisorie… | x_refsource_CONFIRM |
| https://github.com/risc0/risc0/pull/3181 | x_refsource_MISC |
| https://github.com/risc0/zirgen/pull/238 | x_refsource_MISC |
| https://github.com/risc0/risc0/commit/006d86c363b… | x_refsource_MISC |
| https://github.com/risc0/risc0/commit/1873bbb8a56… | x_refsource_MISC |
| https://github.com/risc0/risc0/commit/67f2d81c638… | x_refsource_MISC |
| https://github.com/risc0/zirgen/commit/e0e2918302… | x_refsource_MISC |
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CVE-2025-61588 (GCVE-0-2025-61588)
Vulnerability from cvelistv5 – Published: 2025-10-01 23:30 – Updated: 2025-10-02 18:01
VLAI
Title
risc0 vulnerable to arbitrary code execution in guest via memory safety failure in `sys_read`
Summary
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture. In versions 2.0.2 and below of risc0-zkvm-platform, when the zkVM guest calls sys_read, the host is able to use a crafted response to write to an arbitrary memory location in the guest. This capability can be leveraged to execute arbitrary code within the guest. As sys_read is the mechanism by which input is requested by the guest, all guest programs built with the affected versions are vulnerable. This critically compromises the soundness guarantees of the guest program. Other affected packages include risc0-aggregation versions below 0.9, risc0-zkos-v1compat below 2.1.0, risc0-zkvm versions between 3.0.0-rc.1 and 3.0.1. This issue has been fixed in the following versions: risc0-zkvm-platform 2.1.0, risc0-zkos-v1compat 2.1.0, risc0-aggregation 0.9, and risc0-zkvm 2.3.2 and 3.0.3.
Severity
SSVC
Exploitation: none
Automatable: yes
Technical Impact: total
CISA Coordinator (v2.0.3)
CWE
- CWE-94 - Improper Control of Generation of Code ('Code Injection')
Assigner
References
3 references
| URL | Tags |
|---|---|
| https://github.com/risc0/risc0/security/advisorie… | x_refsource_CONFIRM |
| https://github.com/risc0/risc0/pull/3351 | x_refsource_MISC |
| https://github.com/risc0/risc0/commit/3f00e1fa015… | x_refsource_MISC |
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CVE-2025-54873 (GCVE-0-2025-54873)
Vulnerability from cvelistv5 – Published: 2025-08-05 23:35 – Updated: 2025-08-06 13:53
VLAI
Title
RISC Zero Underconstrained Vulnerability: Division
Summary
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture. RISC packages risc0-zkvm versions 2.0.0 through 2.1.0 and risc0-circuit-rv32im and risc0-circuit-rv32im-sys versions 2.0.0 through 2.0.4 contain vulnerabilities where signed integer division allows multiple outputs for certain inputs with only one being valid, and division by zero results are underconstrained. This issue is fixed in risc0-zkvm version 2.2.0 and version 3.0.0 for the risc0-circuit-rv32im and risc0-circuit-rv32im-sys packages.
Severity
SSVC
Exploitation: none
Automatable: yes
Technical Impact: partial
CISA Coordinator (v2.0.3)
CWE
- CWE-369 - Divide By Zero
Assigner
References
3 references
| URL | Tags |
|---|---|
| https://github.com/risc0/risc0/security/advisorie… | x_refsource_CONFIRM |
| https://github.com/risc0/risc0/pull/3235 | x_refsource_MISC |
| https://github.com/risc0/zirgen/pull/249 | x_refsource_MISC |
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CVE-2025-52484 (GCVE-0-2025-52484)
Vulnerability from cvelistv5 – Published: 2025-06-20 17:21 – Updated: 2025-06-23 15:28
VLAI
Title
RISC Zero zkVM Underconstrained Vulnerability
Summary
RISC Zero is a general computing platform based on zk-STARKs and the RISC-V microarchitecture. Due to a missing constraint in the rv32im circuit, any 3-register RISC-V instruction (including remu and divu) in risc0-zkvm 2.0.0, 2.0.1, and 2.0.2 are vulnerable to an attack by a malicious prover. The main idea for the attack is to confuse the RISC-V virtual machine into treating the value of the rs1 register as the same as the rs2 register due to a lack of constraints in the rv32im circuit. Rust applications using the risc0-zkvm crate at versions 2.0.0, 2.0.1, and 2.0.2 should upgrade to version 2.1.0. Smart contract applications using the official RISC Zero Verifier Router do not need to take any action: zkVM version 2.1 is active on all official routers, and version 2.0 has been disabled. Smart contract applications not using the verifier router should update their contracts to send verification calls to the 2.1 version of the verifier.
Severity
SSVC
Exploitation: none
Automatable: yes
Technical Impact: partial
CISA Coordinator (v2.0.3)
CWE
- CWE-345 - Insufficient Verification of Data Authenticity
Assigner
References
7 references
| URL | Tags |
|---|---|
| https://github.com/risc0/risc0/security/advisorie… | x_refsource_CONFIRM |
| https://github.com/risc0/risc0/pull/3181 | x_refsource_MISC |
| https://github.com/risc0/zirgen/pull/238 | x_refsource_MISC |
| https://github.com/risc0/risc0/commit/006d86c363b… | x_refsource_MISC |
| https://github.com/risc0/risc0/commit/1873bbb8a56… | x_refsource_MISC |
| https://github.com/risc0/risc0/commit/67f2d81c638… | x_refsource_MISC |
| https://github.com/risc0/zirgen/commit/e0e2918302… | x_refsource_MISC |
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