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          "value": "XiangShan (Open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) contains an improper exceptional-condition handling flaw in its CSR subsystem (NewCSR). On affected versions, certain sequences of CSR operations targeting non-existent/custom CSR addresses may trigger an illegal-instruction exception but fail to reliably transfer control to the configured trap handler (mtvec), causing control-flow disruption and potentially leaving the core in a hung or unrecoverable state. This can be exploited by a local attacker able to execute code on the processor to cause a denial of service and potentially inconsistent architectural state."
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          "url": "https://github.com/OpenXiangShan/XiangShan/issues/3959"
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        {
          "url": "https://github.com/OpenXiangShan/XiangShan/pull/3966"
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    "cveId": "CVE-2026-29643",
    "datePublished": "2026-04-20T00:00:00.000Z",
    "dateReserved": "2026-03-04T00:00:00.000Z",
    "dateUpdated": "2026-04-20T21:18:39.405Z",
    "state": "PUBLISHED"
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