{
  "containers": {
    "cna": {
      "affected": [
        {
          "product": "n/a",
          "vendor": "n/a",
          "versions": [
            {
              "status": "affected",
              "version": "n/a"
            }
          ]
        }
      ],
      "descriptions": [
        {
          "lang": "en",
          "value": "A local attacker who can execute privileged CSR operations (or can induce firmware to do so) performs carefully crafted reads/writes to menvcfg (e.g., csrrs in M-mode). On affected XiangShan versions (commit aecf601e803bfd2371667a3fb60bfcd83c333027, 2024-11-19), these menvcfg accesses can unexpectedly set WPRI (reserved) bits in the status view (xstatus) to 1. RISC-V defines WPRI fields as \"writes preserve values, reads ignore values,\" i.e., they must not be modified by software manipulating other fields, and menvcfg itself contains multiple WPRI fields."
        }
      ],
      "problemTypes": [
        {
          "descriptions": [
            {
              "description": "n/a",
              "lang": "en",
              "type": "text"
            }
          ]
        }
      ],
      "providerMetadata": {
        "dateUpdated": "2026-04-20T20:30:19.577Z",
        "orgId": "8254265b-2729-46b6-b9e3-3dfca2d5bfca",
        "shortName": "mitre"
      },
      "references": [
        {
          "url": "https://github.com/OpenXiangShan/XiangShan/issues/3934"
        },
        {
          "url": "https://github.com/OpenXiangShan/XiangShan/commit/5e3dd63"
        },
        {
          "url": "https://docs.riscv.org/reference/isa/priv/priv-csrs.html"
        },
        {
          "url": "https://docs.riscv.org/reference/isa/priv/machine.html"
        }
      ]
    }
  },
  "cveMetadata": {
    "assignerOrgId": "8254265b-2729-46b6-b9e3-3dfca2d5bfca",
    "assignerShortName": "mitre",
    "cveId": "CVE-2026-29642",
    "datePublished": "2026-04-20T00:00:00.000Z",
    "dateReserved": "2026-03-04T00:00:00.000Z",
    "dateUpdated": "2026-04-20T20:30:19.577Z",
    "state": "PUBLISHED"
  },
  "dataType": "CVE_RECORD",
  "dataVersion": "5.2",
  "vulnerability-lookup:meta": {
    "nvd": "{\"cve\":{\"id\":\"CVE-2026-29642\",\"sourceIdentifier\":\"cve@mitre.org\",\"published\":\"2026-04-20T21:16:19.393\",\"lastModified\":\"2026-04-20T21:16:19.393\",\"vulnStatus\":\"Received\",\"cveTags\":[],\"descriptions\":[{\"lang\":\"en\",\"value\":\"A local attacker who can execute privileged CSR operations (or can induce firmware to do so) performs carefully crafted reads/writes to menvcfg (e.g., csrrs in M-mode). On affected XiangShan versions (commit aecf601e803bfd2371667a3fb60bfcd83c333027, 2024-11-19), these menvcfg accesses can unexpectedly set WPRI (reserved) bits in the status view (xstatus) to 1. RISC-V defines WPRI fields as \\\"writes preserve values, reads ignore values,\\\" i.e., they must not be modified by software manipulating other fields, and menvcfg itself contains multiple WPRI fields.\"}],\"metrics\":{},\"references\":[{\"url\":\"https://docs.riscv.org/reference/isa/priv/machine.html\",\"source\":\"cve@mitre.org\"},{\"url\":\"https://docs.riscv.org/reference/isa/priv/priv-csrs.html\",\"source\":\"cve@mitre.org\"},{\"url\":\"https://github.com/OpenXiangShan/XiangShan/commit/5e3dd63\",\"source\":\"cve@mitre.org\"},{\"url\":\"https://github.com/OpenXiangShan/XiangShan/issues/3934\",\"source\":\"cve@mitre.org\"}]}}"
  }
}