CVE-2026-23554 (GCVE-0-2026-23554)

Vulnerability from cvelistv5 – Published: 2026-03-23 06:56 – Updated: 2026-03-23 14:19
VLAI?
Title
Use after free of paging structures in EPT
Summary
The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.
Severity ?
7.8 (High)
CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:H/A:H
CWE
  • CWE-367 - Time-of-check Time-of-use (TOCTOU) Race Condition
Assigner
XEN
References
Impacted products
Vendor Product Version
Xen Xen Unknown: consult Xen advisory XSA-480
Create a notification for this product.
Date Public ?
2026-03-17 12:00
Credits
This issue was discovered by Roger Pau Monné of XenServer.
Show details on NVD website
To clipboard 

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  • Confirmed: The vulnerability has been validated from an analyst's perspective.
  • Published Proof of Concept: A public proof of concept is available for this vulnerability.
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  • Not patched: The vulnerability was not observed as successfully patched by the user who reported the sighting.



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